Memory Access Schemes for Configurable Processors

  • Holger Lange
  • Andreas Koch
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1896)


This work discusses theMemoryArchitecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configurable caches) and regular accesses (via pre-fetching stream buffers). By hiding specifics behind a consistent abstract interface, it is suitable as a target environment for automatic hardware compilation.


Cache Line Memory Architecture Port Interface Datapath Architecture Stream Port 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Amerson, R., “Teramac — Configurable Custom Computing”, Proc. IEEE Symp. on FCCMs, Napa 1995Google Scholar
  2. 2.
    Bertin, P., Roncin, D., Vuillemin, J., “Programmable Active Memories: A Performance Assessment”, Proc. Symp. Research on Integrated Systems, Cambridge (Mass.) 1993Google Scholar
  3. 3.
    Box, B., “Field-Programmable Gate Array-based Reconfigurable Preprocessor”, Proc. IEEE Symp. on FCCMs, Napa 1994Google Scholar
  4. 4.
    Buell, D., Arnold, J., Kleinfelder, W., “Splash 2 — FPGAs in Custom Computing Machines”, IEEE Press, 1996Google Scholar
  5. 5.
    Rupp, C., Landguth, M., Garverick, et al., “The NAPA Adaptive Processing Architecture”, Proc. IEEE Symp. on FCCMs, Napa 1998Google Scholar
  6. 6.
    Hauser, J., Wawrzynek, J., “Garp: A MIPS Processor with a Reconfigurable Coprocessor”, Proc. IEEE Symp. on FCCMs, Napa 1997Google Scholar
  7. 7.
    Wittig, R., Chow, P., “OneChip: An FPGA Processor with Reconfigurable Logic”, Proc. IEEE Symp. on FCCMs, Napa 1996Google Scholar
  8. 8.
    Jacob, J., Chow, P., “Memory Interfacing and Instruction Specification for Reconfigurable Processors”, Proc. ACM Intl. Symp. on FPGAs, Monterey 1999Google Scholar
  9. 9.
    Triscend, “Triscend E5 CSoC Family”,, 2000
  10. 10.
    Altera, “Excalibur Embedded Processor Solutions”,, 2000
  11. 11.
    TSI-Telsys, “ACE2card User’s Manual”, hardware documentation, 1998Google Scholar
  12. 12.
    Koch, A., “A Comprehensive Platform for Hardware-Software Co-Design”, Proc. Intl. Workshop on Rapid-Systems Prototyping, Paris 2000Google Scholar
  13. 13.
    Annapolis Microsystems,, 2000
  14. 14.
    Virtual Computer Corp.,, 2000
  15. 15.
    Callahan, T., Hauser, J.R., Wawrzynek, J., “The Garp Architecture and C Compiler”, IEEE Computer, April 2000Google Scholar
  16. 16.
    Li, Y., Callahan, T., Darnell, E., Harr, R., etal., “Hardware-Software Co-Design of Embedded Reconfigurable Architectures”, Proc. 37th Design Automation Conference, 2000Google Scholar
  17. 17.
    Gokhale, M.B., Stone, J.M., “NAPAC: Compiling for a Hybrid RISC/FPGA Machine”, Proc. IEEE Symp. on FCCMs, 1998Google Scholar
  18. 18.
    Koch, A., Golze, U., “Practical Experiences with the SPARXIL Co-Processor”, Proc. Asilomar Conference on Signals, Systems, and Computers, 11/1997Google Scholar
  19. 19.
    Fung, J.M.L.F., Pan, J., “Configurable Cache”, CMU EE742 course project,, 1998
  20. 20.
    McKee, S.A., “Maximizing Bandwidth for Streamed Computations”, dissertation, U. of Virginia, School of Engineering and Applied Science, 1995Google Scholar
  21. 21.
    Sun Microelectronics, “microSPARC-IIep User’s Manual”,, 1997
  22. 22.
    Weaver, D.L., Germond, T., “The SPARC Architecture Manual, Version 8”, Prentice-Hall, 1992Google Scholar
  23. 23.
    PLX Technology, “PCI 9080 Data Book”,, 1998
  24. 24.
    Xilinx, Inc., “Virtex 2.5V Field-Programmable Gate Arrays”,, 1999
  25. 25.
    Xilinx, Inc. “Designing Flexible, Fast CAMs with Virtex Family FPGAs”, Xilinx Application Note 203, 1999Google Scholar
  26. 26.
    Hennessy, J., Patterson, D., “Computer Architecture: A Quantitative Approach”, Morgan-Kaumann, 1990Google Scholar
  27. 27.
    Zhong, P., Martonosi, M., “Using Reconfigurable Hardware to Customize Memory Hierarchies”, Proc. SPIE, vol. 2914, 1996Google Scholar
  28. 28.
    Kimura, S., Yukishita, M., Itou, Y., et al., “A Hardware/Software Codesign Method for a General-Purpose Reconfigurable Co-Processor”, Proc. 5th CODES/CASHE, 1997Google Scholar
  29. 29.
    Carter, J., Hsieh, W., Stoller, L., et al., “Impulse: Building a Smarter Memory Controller”, Proc. 5th Intl. Symp. on High. Perf. Comp. Arch. (HPCA), 1999Google Scholar
  30. 30.
    Nakkar, M., Harding, J., Schwartz, D., et al., “Dynamically programmable cache”, Proc. SPIE, vol. 3526, 1998Google Scholar
  31. 31.
    Zhang, X., Dasdan, A., Schulz, M., et al., “Architectural Adaptation for Application-Specific Locality Optimizations”, Proc. Intl. Conf. on Comp. Design (ICCD), 1997Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Holger Lange
    • 1
  • Andreas Koch
    • 1
  1. 1.Tech. Univ. Braunschweig (E.I.S.)BraunschweigGermany

Personalised recommendations