A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization
Internet Protocol (IP) characterization is the process of classifying IP packets into categories, mainly depending on information in the header. This report describes the implementation of an FPGA-based dynamically reconfigurable Content Addressable Memory (CAM) for IP version 6 (IPv6) characterization. This CAM is characterized by a large width of the search word, a relatively small number of CAM words (i.e. several 100’s) and the fact that these words may contain ‘don’t cares’. The CAM is updated by dynamic reconfiguration and has a novel architecture that allows the space, that each single CAM word occupies, to be variable. A priority mechanism has been developed which allows also to explicitly assign a priority to a CAM entry. This way, CAM words can be added/deleted in a more efficient way.
KeywordsField Programmable Gate Array Internet Protocol Match Block Destination Address Internet Protocol Address
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