Verification of Dynamically Reconfigurable Logic

  • David Robinson
  • Patrick Lysaght
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1896)


Conventional FPGA design assumes a one-to-one mapping between circuits and device resources. In contrast, dynamically reconfigurable designs map many circuits to shared device resources. Each many-to-one mapping can be decomposed into sequences of temporal, one-to-one mappings. The verification of dynamically reconfigurable logic is complicated by the need to verify that each constituent mapping is correct and that its sequencing with respect to time and other circuits is also correct. In this paper, we introduce new design tools for verifying dynamically reconfigurable logic. The tools extend the capabilities of the Dynamic Circuit Switching (DCS) CAD framework for dynamically reconfigurable logic. The verification capabilities include new design rule checks, design violation monitoring, and the extension of coverage analysis and performance profiling techniques to dynamically reconfigurable designs.


Active Monitor Test Vector Dynamic Task Dynamically Reconfigurable Reconfiguration Controller 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    Avant! Corporation, “Formal Techniques Help Shoulder the Verification Burden” Electronics Journal Technical, Aug. 1998!/EJ/Technical/Articles/Item/0,1058,88,00.html
  2. [2]
    B. L. Hutchings, “Exploiting Reconfigurability Through Domian-Specific Systems”, in Field-Programmable Logic and Applications, W. Luk, P.Y.K Cheung and M. Glesner (editors), pp. 193–202, London, England, Sept 1997Google Scholar
  3. [3]
    D. Robinson, G. McGregor and P. Lysaght, “New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic”, in Field Programmable Logic and Applications, R. Hartenstein and A. Keevallik (Eds.), pp 1–8, Tallinn, Estonia, Sept. 1998Google Scholar
  4. [4]
    P. Lysaght and J. Stockwood, “A Simulation Tool for Dynamically Reconfigurable Field Programmable Gate Arrays”, in IEEE Transactions on VLSI Systems, Vol. 4, No. 3, pp. 381–390, 1996CrossRefGoogle Scholar
  5. [5]
    D. Robinson and P. Lysaght, “Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems using the DCS CAD Framework”, in Field Programmable Logic and Applications, P. Lysaght, J. Irvine and R. Hartenstein (Eds.), pp 41–50, Glasgow, Scotland, Aug. 1999Google Scholar
  6. [6]
    W. Luk, N. Shirazi and P.Y.K. Cheung, “Modelling and Optimising Run-time Reconfigurable Systems”, in IEEE Symposium on Field Programmable Custom Computing Machines, K. L. Pocek and J. Arnold (Eds.), pp. 167–176., Los Alamitos, California, USA, April 1996Google Scholar
  7. [7]
    D. Gibson, M. Vasilko and D. Long, “Virtual Prototyping for Dynamically Reconfigurable Architectures using Dynamic Generic Mapping”, in Proceedings of VIUF Fall’ 98, Orlando, Florida, USA, Oct. 1998Google Scholar
  8. [8]
    M. Vasilko and D. Cabanis, “A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy”, in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Nov. 1999Google Scholar
  9. [9]
    Gordon Brebner, “CHASTE: a Hardware/Software Co-design Testbed for the Xilinx XC6200”, in Reconfigurable Architectures Workshop, R. W. Hartenstein and V. K. Prasanna (Eds.), Geneva, Switzerland, April 1997Google Scholar
  10. [10]
    K. W. Susanto and T. Melham, “Formally Analysed Dynamic Synthesis of Hardware”, in Theorem Proving in Higher Order Logics: Emerging Trends: 11th International Conference (TPHOLs’98), Canberra, Australia, Sept. 1998Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • David Robinson
    • 1
  • Patrick Lysaght
    • 1
  1. 1.Dept. Electronic and Electrical EngineeringUniversity of StrathclydeGlasgowUK

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