Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
Model checking 6 13 is an automated procedure for determining whether a finite state program satisfies a temporal property.Model checking tools, due to the complex nature of the specification methods, are used most effectively by verification experts. In order to make these tools more accessible to non-expert users, who may not be familiar with these formal notations, we need to make model checkers easier to use. Visually intuitive specification methods may provide an alternative way to specify temporal behavior.
KeywordsModel Check Regular Language Timing Diagram Proof Obligation Symbolic Timing
- 1.N. Amla, E.A. Emerson, R.P. Kurshan, and K.S. Namjoshi. Model checking synchronous timing diagrams. In FMCAD, volume 1954 of LNCS, 2000.Google Scholar
- 2.N. Amla, E.A. Emerson, K. Namjoshi, and R. Trefler. Assume-guarantee based compositional reasoning for synchronous timing diagrams. In TACAS, volume 2031 ofLNCS, 2001.Google Scholar
- 3.T. Amon, G. Borriello, T. Hu, and J. Liu. Symbolic Timing Verification of Timing Diagrams Using Presburger Formulas. In DAC, 1997.Google Scholar
- 4.A. Benveniste. Safety Critical Embedded Systems Design: the SACRES approach. Technical report, INRIA, May 1998. URL: http://www.tni.fr/sacres/index.html.
- 5.U. Brockmeyer and G. Wittich. Tamagotchis need not die-Verification of STATEMATE Designs. In TACAS. Springer-Verlag, March 1998.Google Scholar
- 6.E. M. Clarke and E. A. Emerson. Design and Synthesis of Synchronization Skeletons using Branching Time Temporal Logic. In Workshop on Logics of Programs, volume 131. Springer Verlag, 1981.Google Scholar
- 7.W. Damm, B. Josko, and Rainer Schlör. Specification and Verification of VHDL-based System-level Hardware Designs. In Egon Borger, editor, Specification and Validation Methods. Oxford University Press, 1994.Google Scholar
- 8.K. Fisler. Containment of Regular Languages in Non-Regular Timing Diagrams Languages is Decidable. In CAV. Springer Verlag, 1997.Google Scholar
- 9.K. Fisler. On Tableau Constructions for Timing Diagrams. In NASA Langley Workshop on Formal Methods, 2000.Google Scholar
- 10.R.H. Hardin, Z. Har’el, and R.P. Kurshan. COSPAN. In CAV, volume 1102 of LNCS, 1996.Google Scholar
- 11.J. Helbig, R. Schlor, W. Damm, G. Dohmen, and P. Kelb. VHDL/S-integrating statecharts, timing diagrams, and VHDL. Microprocessing and Microprogramming, 38, 1993.Google Scholar
- 12.PCI Special Interest Group. PCI Local Bus Specification Rev 2.1. Technical report, December 1998.Google Scholar
- 13.J.P. Queille and J. Sifakis. Specification and Verification of Concurrent Systems in CESAR. In Proc. of the 5th International Symposium on Programming, volume 137 of LNCS, 1982.Google Scholar