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Adaptively Mapping Code in an Intelligent Memory Architecture

  • Yan Solihin
  • Jaejin Lee
  • Joseph Torrellas
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2107)

Abstract

This paper presents an algorithm to automatically map code to a generic Processor-In-Memory (PIM) system that consists of a host processor and a much simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, processors should overlap their execution as much as possible.

Our algorithm is embedded in a compiler and run-time system and maps applications fully automatically using both static and dynamic information. Using a set of applications and a simulated architecture, we show average speedups of 1.7 over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited, and represents one step toward effectively mapping code to more advanced PIM systems.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Yan Solihin
    • 1
    • 3
  • Jaejin Lee
    • 2
  • Joseph Torrellas
    • 1
  1. 1.Michigan State UniversityMichigan
  2. 2.University of Illinois at Urbana-ChampaignIllinois
  3. 3.Los Alamos National LaboratoryLos Alamos

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