On Model Checking Synchronised Hardware Circuits

  • Martin Leucker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1961)

Abstract

In this paper, we present a framework for specifying and verifying an important class of hardware systems. These systems are build up from a parallel composition of circuits switching by a global clock. They can equivalently be characterised by Petri nets with a maximal step semantics. As a semantic model for these systems we introduce Distributed Synchronous Transition Systems (DSTS) which are distributed transition systems with a global clock synchronising the executions of actions. We show the relations to asynchronous behaviour of distributed transition systems emplyoing Mazurkiewicz trace theory which allows a uniform treatment of synchronous as well as asynchronous executions. We introduce a process algebra like calculus for defining DSTS which we call Synchronous Process Systems. Furthermore, we present Foata Lineartime Temporal Logic (FLTL) which is a temporal logic with a flavour of LTL adapted for specifying properties of DSTS. Our important contributions are the developed decision procedures for satisfiability as well as model checking of FLTL formulas, both based on alternating Büchi automata.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Martin Leucker
    • 1
  1. 1.RWTH AachenLehrstuhl für Informatik IIAachenGermany

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