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Checking Safety Properties Using Induction and a SAT-Solver

  • Mary Sheeran
  • Satnam Singh
  • Gunnar Stålmarck
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1954)

Abstract

We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-solver. We describe some novel induction-based methods, and show how they are related to more standard fixpoint algorithms for invariance checking. We also present preliminary experimental results in the verification of FPGA cores. This demonstrates the practicality of combining a SAT-solver with induction for safety property checking of hardware in a real design flow.

Keywords

Model Check Transition Relation Safety Property Reachable State Symbolic Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Mary Sheeran
    • 1
    • 2
  • Satnam Singh
    • 3
  • Gunnar Stålmarck
    • 1
    • 2
  1. 1.Prover Technology ABStockholmSweden
  2. 2.Chalmers University of TechnologyGöteborgSweden
  3. 3.Xilinx Inc.San JoseUSA

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