Executable Protocol Specification in ESL

  • E. Clarke
  • S. German
  • Y. Lu
  • H. Veith
  • D. Wang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1954)

Abstract

Hardware specifications in English are frequently ambiguous and often self-contradictory.We propose a new logic ESL which facilitates formal specification of hardware protocols.Our logic is closely related to LTL but can express all regular safety properties. We have developed a protocol synthesis methodology which generates Mealy machines from ESL specifications. The Mealy machines can be automatically translated into executable code either in Verilog or SMV. Our methodology exploits the observation that protocols are naturally composed of many semantically distinct components. This structure is reflected in the syntax of ESL specifications.We use a modified LTL tableau construction to build a Mealy machine for each component. The Mealy machines are connected together in a Verilog or SMV framework. In many cases this makes it possible to circumvent the state explosion problem during code generation and to identify conflicts between components during simulation or model checking.We have implemented a tool based on the logic and used it to specify and verify a significant part of the PCI bus protocol.

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References

  1. 1.
    Y. Abarbanel, I. Beer, L. Gluhovsky, S. Keidar and Y. Wolfsthal,“FoCs-AutomaticGeneration of Simulation Checkers from Formal Specifications”, CAV 00: Computer-Aided Verification, Lecture Notes in Computer Science 1855, 538–542. Springer-Verlag, 2000.CrossRefGoogle Scholar
  2. 2.
    R. Alur and T.A. Henzinger. Reactive Modules, Proceedings of the 11th Annual Symposium on Logic in Computer Science, 207–218. IEEE Computer Society Press, 1996.Google Scholar
  3. 3.
    R. Alur, T.A. Henzinger, and O. Kupferman. Alternating-time temporal logic. In Proc. 38th IEEE Symposium on Foundations of Computer Science, 100–109, 1997.Google Scholar
  4. 4.
    R. E. Bryant, P. Chauhan, E. M. Clarke, A. Goel. A Theory of Consistency for Modular Synchronous Systems. Formal Methods in Computer-Aided Design, 2000Google Scholar
  5. 5.
    P. Chauhan, E. Clarke, Y. Lu, and D. Wang. Verifying IP-Core based System-On-Chip Designs. In Proceedings of the IEEE ASIC Conference, 27–31, 1999.Google Scholar
  6. 6.
    T. Cormen, C. Leiserson, and R. Rivest. Introduction to Algorithm. MIT Press, 1990.Google Scholar
  7. 7.
    E. Clarke and E. Emerson. Synthesis of synchronization skeletons for branching time temporal logic. Logic of Programs: Workshop, Yorktown Heights, NY, May 1981 Lecture Notes in Computer Science, Vol. 131, Springer-Verlag. 1981.Google Scholar
  8. 8.
    E. Emerson and E. Clarke.Using branching time temporal logic to synthesize synchronization skeletons. In Science of Computer Programming, Vol 2, 241–266. 1982.MATHGoogle Scholar
  9. 9.
    E. Clarke, O. Grumberg, and D. Peled. Model Checking.MIT Publishers, 1999.Google Scholar
  10. 10.
    David Dill. Trace Theory for Automatic Hierarchical Verification of Speed-independentCircuits. MIT Press, 1989.Google Scholar
  11. 11.
    M. Fujita and S. Kono. Synthesis of Controllers from Interval Temporal Logic Specification. InternationalWorkshop on Logic Synthesis,May, 1993.Google Scholar
  12. 12.
    D. Gabbay. The Declarative Past and Imperative Future: Executable Temporal Logic for Interactive Systems. In B. Banieqbal, B. Barringer, and A. Pnueli, editors, Temporal Logic in Specification,Vol. 398, 409–448. Springer Verlag, LNCS 398, 1989.Google Scholar
  13. 13.
    R. Gerth, D. Peled, M. Y. Vardi, and P. Wolper. Simple on-the-fly automatic verification of linear temporal logic. In Proc. 15th Work. Protocol Specification, Testing, and Verification, Warsaw, June 1995. North-Holland.Google Scholar
  14. 14.
    N. Halbwachs, J.-C. Fernandez, and A. Bouajjanni. An executable temporal logic to express safety properties and its connection with the language Lustre. In Sixth International Symp. on Lucid and Intensional Programming, ISLIP’93, Quebec City, Canada, April 1993. Universit’e Laval.Google Scholar
  15. 15.
    L. Lamport. The temporal logic of actions. ACM TOPLAS, 16(3):872–923,March 1994.CrossRefGoogle Scholar
  16. 16.
    Z. Manna, P. Wolper: Synthesis of Communicating Processes from Temporal Logic Specifications, ACM TOPLAS, Vol.6, N.1, Jan. 1984, 68–93.MATHCrossRefGoogle Scholar
  17. 17.
    K.L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.Google Scholar
  18. 18.
    B. Moszkowski. Executing temporal logic programs. Cambridge University Press, 1986.Google Scholar
  19. 19.
    PCI Special Interest Group. PCI Local Bus Specification Rev 2.2. Dec. 1998.Google Scholar
  20. 20.
    J. Yuan, K. Shultz, C. Pixley, and H. Miller. Modeling Design Constraints and Biasing in Simulation Using BDDs. In International Conference on Computer-Aided Design. 584–589, November 7-11, 1999Google Scholar
  21. 21.
    A. Seawright, and F. Brewer. Synthesis from Production-Based Specifications. In Proceedings of the 29th ACM/IEEE Design Automation Conference, 194–199, 1992.Google Scholar
  22. 22.
    X. Shen, and Arvind. Design and Verification of Speculative Processors. In Proceedings of the Workshop on Formal Techniques for Hardware and Hardware-like Systems, June 1998, Marstrand, Sweden.Google Scholar
  23. 23.
    K. Shimizu, D. Dill, and A. Hu. Monitor Based Formal Specification of PCI. FormalMethods in Computer-Aided Design, 2000.Google Scholar
  24. 24.
  25. 25.
    M. Sipser. Introduction to the Theory of Computation. PWS Publishing Company. 1997.Google Scholar

Copyright information

© Springer-VerlagBerlin Heidelberg 2000

Authors and Affiliations

  • E. Clarke
    • 1
  • S. German
    • 2
  • Y. Lu
    • 1
  • H. Veith
    • 1
    • 3
  • D. Wang
    • 1
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.IBM T. J.Watson Research CenterUSA
  3. 3.TU ViennaUSA

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