Use of Particle Swarm Optimization to Design Combinational Logic Circuits

  • Carlos A. Coello Coello
  • Erika Hernández Luna
  • Arturo Hernández Aguirre
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2606)


This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gatelevel. The proposed algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that particle swarm optimization may be a viable alternative to design combinational circuits at the gate-level.


Genetic Algorithm Particle Swarm Optimization Truth Table Human Designer Arithmetic Circuit 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Carlos A. Coello Coello
    • 1
  • Erika Hernández Luna
    • 1
  • Arturo Hernández Aguirre
    • 2
  1. 1.Depto. Ing. Eléctrica, Sección de Computación Av. Instituto Politécnico Nacional No. 2508CINVESTAV-IPN, Evolutionary Computation GroupMéxicoMexico
  2. 2.CIMAT, Area de ComputaciónCallejón Jalisco s/n Mineral de Valenciana, GuanajuatoGuanajuatoMexico

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