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An Optimized S-Box Circuit Architecture for Low Power AES Design

  • Sumio Morioka
  • Akashi Satoh
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2523)

Abstract

Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 μW at 10 MHz using 0.13 μm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 μW, respectively.

Keywords

Power Consumption Advance Encryption Standard Composite Field Galois Field Circuit Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Sumio Morioka
    • 1
  • Akashi Satoh
    • 1
  1. 1.IBM ResearchTokyo Research Laboratory, IBM Japan Ltd.Yamato-shi, Kanagawa-kenJapan

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