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2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis

  • A.K. Lutz
  • J. Treichler
  • F.K. Gürkaynak
  • H. Kaeslin
  • G. Basler
  • A. Erni
  • S. Reichmuth
  • P. Rommens
  • S. Oetiker
  • W. Fichtner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2523)

Abstract

We present and evaluate efficient VLSI implementations of both Rijndael and Serpent. The two cipher algorithms have been implemented by two comparable design teams within the same timeframe using the same fabrication process and EDA tools. We are thus in a position to compare to what degree the Rijndael and Serpent ciphers are suitable for dedicated hardware architectures. Both ASICs support encryption as well as decryption in ECB mode and include on-chip subkey generation. The two designs have been fabricated in a 0.6μm 3LM CMOS technology. Measurement results verified an encryption and decryption throughput of 2.26Gbit/s and 1.96Gbit/s for Rijndael and Serpent respectively. Circuit complexity is in the order of 300k transistors in either case.

Keywords

Data Block Advance Encryption Standard Multiplicative Inverse Advance Encryption Standard Algorithm Serpent Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • A.K. Lutz
    • 1
  • J. Treichler
    • 1
  • F.K. Gürkaynak
    • 2
  • H. Kaeslin
    • 3
  • G. Basler
    • 1
  • A. Erni
    • 1
  • S. Reichmuth
    • 1
  • P. Rommens
    • 1
  • S. Oetiker
    • 2
  • W. Fichtner
    • 2
  1. 1.Department of Information Technology and Electrical EngineeringETH ZürichZürichSwitzerland
  2. 2.Integrated Systems Laboratory Department of Information Technology and Electrical EngineeringETH ZürichZürichSwitzerland
  3. 3.Microelectronics Design CenterETH ZürichZürichSwitzerland

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