Exploiting Data Value Prediction in Compiler Based Thread Formation

  • Anasua Bhowmik
  • Manoj Franklin
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2552)


Speculative multithreading (SpMT) is an effective execution model for parallelizing non-numeric programs, which tend to use irregular and pointer-intensive data structures, and have complex flows of control. An SpMT compiler performs program partitioning by carefully considering the data dependencies present in the program. However, at run-time, the data dependency picture changes dramatically if the SpMT hardware performs data value prediction. Many of the data dependencies, which guided the compiler’s partitioning algorithm in taking decisions, may lose their relevance due to successful data value prediction. This paper presents a compiler framework that uses profile-based value predictability information when making program partitioning decisions. We have developed a Value Predictability Profiler (VPP) that generates the value prediction statistics for the source variables in a program. Our SpMT compiler utilizes this information by ignoring the data dependencies due to variables with high prediction accuracies. The compiler can thus perform more efficient thread formation. This SpMT compiler framework is implemented on the SUIF-MachSUIF platform. A simulation-based evaluation of SPEC programs shows that the speedup with 6 processing elements increases up to 21% when utilizing value predictability information during program partitioning.


data dependency data value prediction parallelization profiling speculative multithreading (SpMT) thread-level parallelism (TLP) 


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  1. [1]
    A. Bhowmik and M. Franklin, “A General Compiler Framework for Speculative Multithreading,” Proc. 14th ACM Symp. on Parallel Algorithms and Architectures (SPAA 2002). 507, 508, 510, 511Google Scholar
  2. [2]
    C-Y. Fu, M. D. Jennings, S. Larin, and T.M. Conte, “Value Speculation Scheduling for High Performance Processor,” Proc. ASPLOS-VIII, 1998. 507Google Scholar
  3. [3]
    M.W. Hall, et al, “Maximizing Multiprocessor Performance with the SUIF Compiler,” IEEE Computer, December 1996. 509Google Scholar
  4. [4]
    O.C. Maquelin, H.H. J. Hum, and G.R. Gao, “Costs and Benefits of Multithreading with Off-the-Shelf RISC Processor,” Proc. 1st Int’l EURO-PAR Conf., 1995. 507Google Scholar
  5. [5]
    P. Marcuello, J. Tubella and A. Gonzalez, “Value Prediction for Speculative Multithreaded Architectures,” Proc. 32nd Int’l Symp. on Microarchitecture, 1998. 507, 508Google Scholar
  6. [6]
    K. Olukotun, et al, “A Chip-Multiprocessor Architecture with Speculative Multithreading,” IEEE Transactions on Computers, September 1999.Google Scholar
  7. [7]
    J-Y. Tsai and P-C. Yew, “The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dendence Checking and Control Speculation,” Proc. Int’l Conf. on Parallel Architectures and Compilation Techniques (PACT), 1996. 507Google Scholar
  8. [8]
    T.N. Vijaykumar and G. S. Sohi, “Task Selection for a Multiscalar Processor,” Proc. 31st Int’l Symp. on Microarchitecture (MICRO-31), 1998. 507Google Scholar
  9. [9]
    K. Wang and M. Franklin, “Highly Accurate Data Value Prediction using Hybrid Predictors,” Proc. 30th Int’l Symp. on Microarchitecture (MICRO-30), pp. 281–290, 1997. 512Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Anasua Bhowmik
    • 1
  • Manoj Franklin
    • 2
  1. 1.Computer Science DepartmentUSA
  2. 2.ECE Department and UMIACSUniversity of MarylandCollege Park

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