Test-pattern generation for VLSI circuits in a Prolog environment
Prolog eminently supports hierarchical development and mixing of descriptions at various hierarchical levels. This fact can be used in test-pattern generation by mixing the functional and implementation specifications of various modules. Only the modules that are faulty need to be expanded to their implementations and a functional description of all the other modules can be used, resulting in considerable gain in efficiency.
High-level fault injection can be easily implemented in Prolog by a hierarchical naming convention described in the paper.
Concurrent fault simulation can be viewed as an optimization of the Prolog control strategy and by saving some select (non-masking) results from previous computations, the wasteful recomputations can be avoided.
Subject IndexTesting Automatic test-pattern generation Logic programming Simulation
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