Using the temporal logic programming language Tokio for algorithm description and automatic CMOS gate array synthesis
To date, simulation has been the primary method used to support hardware logic design. In particular, there has been little that could support such design from the system level, such as a language to describe processing algorithms. In this paper, we will propose a silicon compiler, which is designed to support CMOS gate arrays from the system level. Descriptions from the system level through the state diagram level are done by using the temporal logic programming language called Tokio. Being based on temporal logic, Tokio enables the use of temporal operators. This facilitates the description of concurrent operations that cannot be easily described in Prolog. In addition, because the mathematical models are clearly defined, verification and synthesis can be easily supported. At present, only a simulator coded in Prolog is available to support descriptions of this level in Tokio.
A program that automatically synthesizes logical circuits for CMOS gate array from state diagram level is supported. The core of this program has already been developed in C-Prolog. Synthesis has already been tested at our laboratory. We used the Unify Processor (UP) of PIE (Parallel Inference Machine) which is currently under development, as an example.
This paper introduces the hardware design support strategy based on Tokio, and explains the details of the program that synthesizes CMOS gate arrays from the descriptions of the state diagram level.
KeywordsTemporal Logic Logical Circuit Common Part Linear Time Temporal Logic Gate Count
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