Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System

  • Seung Wook Lee
  • Jong Tae Kim
  • Hongmoon Wang
  • Dae Jin Bae
  • Keon Myung Lee
  • Jee Hyung Lee
  • Jae Wook Jeon
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4251)

Abstract

Context-aware systems, such as intelligent home-care systems or mobile communication devices that are aware of the channel environment, need reasoning ability with numerous rules to manage the current context. Reasoning techniques based on rule-based systems can be used for the efficient reasoning method of these numerous rules. The RETE algorithm has been used for the matching of reasoning rules in rule-based systems. However, the characteristics of the RETE algorithm cause it to have poor performance in Von Neumann computer systems. In this paper, we propose a novel architecture for the RETE network hardware accelerator, which provides efficient reasoning processing performance. Using the parallel RETE network hardware architecture, this accelerator can overcome the architectural constraints imposed by Von Neumann computer systems.

Keywords

Language Code Match Operation Switching Controller Multiprocessor Platform Architectural Constraint 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Seung Wook Lee
    • 1
  • Jong Tae Kim
    • 1
  • Hongmoon Wang
    • 1
  • Dae Jin Bae
    • 1
  • Keon Myung Lee
    • 2
  • Jee Hyung Lee
    • 1
  • Jae Wook Jeon
    • 1
  1. 1.School of Information and Communication EngineeringSungkyunkwan UniversityKorea
  2. 2.School of Electrical and Computer EngineeringChungbuk National UniversityKorea

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