A Framework for Estimating Peak Power in Gate-Level Circuits

  • Diganchal Chakraborty
  • P. P. Chakrabarti
  • Arijit Mondal
  • Pallab Dasgupta
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)


This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS’89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.


Peak Power Primary Input Binary Decision Diagram Partial Assignment Sequential Circuit 
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  1. 1.
    Devadas, S., Keutzer, K., White, J.: Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation. IEEE Transactions on Computer Aided Design 11(3), 373–383 (1992)CrossRefGoogle Scholar
  2. 2.
    Wang, C., Roy, K., Chou, T.: Maximum Power Estimation for Sequential Circuits Using a Test Generation Based Technique. In: Proceedings of the IEEE 1996, Custom Integrated Circuits Conference, pp. 229–232 (1996)Google Scholar
  3. 3.
    Bahar, R., et al.: Algebraic Decision Diagrams and their Applications. Formal Methods in System Design 10(2-3), 171–206 (1997)CrossRefGoogle Scholar
  4. 4.
    Manne, S., Pardo, A., Bahar, R., Hachtel, G., Somenzi, F., Macii, E., Poncino, M.: Computing the Maximum Power Cycles of a Sequential Circuit. In: Proceedings of the 32nd ACM/IEEE conference on Design automation, pp. 23–28 (1995)Google Scholar
  5. 5.
    Mondal, A., Chakrabarti, P.P., Mandal, C.R.: A New Approach to Timing Analysis using Event Propagation and Temporal Logic. In: Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE 2004), pp. 1198–1203 (2004)Google Scholar
  6. 6.
    Yalcin, H., Hayes, J.P.: Event Propagation Conditions in Circuit Delay Computation. ACM Transactions on Design Automation of Electronic Systems (TODAES) 2(3), 249–280 (1997)CrossRefGoogle Scholar
  7. 7.
    Bergman, S., Eliezer, L.L.: A Fast Algorithm for MaxSAT Approximation. In: Proceedings of the Sixth International Conference on Theory and Applications of Satisfiability Testing, Portofino, Italy, pp. 424–431 (2003)Google Scholar
  8. 8.
    Hstad, J.: Some Optimal Inapproximability results. In: Proceedings of the twenty-ninth annual ACM symposium on Theory of computing, pp. 1–10 (1997)Google Scholar
  9. 9.
    Papadimitriou, C.H., Yannakakis, M.: Optimization, approximation, and complexity classes. Journal of Computing and System Sciences 43, 425–440 (1991)zbMATHCrossRefMathSciNetGoogle Scholar
  10. 10.
    Somenzi, F.: Department of Electrical and Computer Engineering, University of Colorado at Boulder (Fabio@Colorado.EDU), CUDD: CU Decision Diagram Package Release 2.4.1,
  11. 11.
    Nilsson, N.J.: Artificial Intelligence: A New Synthesis. Elsevier, Amsterdam (1998)zbMATHGoogle Scholar
  12. 12.
    Brglez, F., Bryan, D., Kozminski, K.: Combinational profiles of sequential benchmark circuits. In: Proceedings of the IEEE International Symposium on Circuits And Systems, pp. 1929–1934 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Diganchal Chakraborty
    • 1
  • P. P. Chakrabarti
    • 1
  • Arijit Mondal
    • 1
  • Pallab Dasgupta
    • 1
  1. 1.Indian Institute of Technology KharagpurIndia

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