Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations

  • Bart R. Zeydel
  • Vojin G. Oklobdzija
Conference paper

DOI: 10.1007/11847083_13

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)
Cite this paper as:
Zeydel B.R., Oklobdzija V.G. (2006) Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. In: Vounckx J., Azemard N., Maurine P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg

Abstract

This paper analyzes the issues that face digital circuit design methodologies and tools which address energy-efficient digital circuit sizing. The best known techniques for resolving these issues are presented, along with the sources of error. The analysis demonstrates that input slope independent models for energy and delay and stage based optimization are effective for analyzing and optimizing energy-efficient digital circuits when applied correctly.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Bart R. Zeydel
    • 1
  • Vojin G. Oklobdzija
    • 1
  1. 1.Advanced Computer Systems Engineering LaboratoryUniversity of California, DavisDavisUSA

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