Supporting Cache Locality Optimization with a Toolset

  • Jie Tao
  • Wolfgang Karl
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4128)

Abstract

Cache performance significantly influences the computation power of modern processors. With the trend of microprocessor design for both general use and embedded systems towards chip-multiple, cache performance becomes more important because an off-chip access is rather expensive in comparison with on-chip references. This means cache locality optimization remains a hot research area for the next generation of computer architectures.

In this paper we present a tool environment aiming at providing the programmers sufficient support in the task of optimizing source codes for better runtime cache behavior. This environment contains a set of tools ranging from profiling, analysis, and simulation tools for gathering performance data, to visualization tools for graphical presentation and platforms for program development. Together, these tools establish a feedback loop for tuning cache performance on current and emerging uniprocessor and multiprocessor systems.

Keywords

Coherence Padding Fist 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Jie Tao
    • 1
  • Wolfgang Karl
    • 1
  1. 1.Institut für Technische InformatikUniversität Karlsruhe (TH)KarlsruheGermany

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