On Interleaving in Timed Automata

  • Ramzi Ben Salah
  • Marius Bozga
  • Oded Maler
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4137)

Abstract

We propose a remedy to that part of the state-explosion problem for timed automata which is due to interleaving of actions. We prove the following quite surprising result: the union of all zones reached by different interleavings of the same set of transitions is convex. Consequently we can improve the standard reachability computation for timed automata by merging such zones whenever they are encountered. Since passage of time distributes over union, we can continue the successor computation from the new zone and eliminate completely the explosion due to interleaving.

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References

  1. [AD94]
    Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science 126, 183–235 (1994)CrossRefMathSciNetMATHGoogle Scholar
  2. [BJJY98]
    Bengtsson, J., Jonsson, B., Lilius, J., Yi, W.: Partial Order Reductions for Timed Systems. In: Sangiorgi, D., de Simone, R. (eds.) CONCUR 1998. LNCS, vol. 1466, pp. 485–500. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  3. [BBM03]
    Ben Salah, R., Bozga, M., Maler, O.: On Timing Analysis of Combinational Circuits. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, pp. 204–219. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  4. [BBM06]
    Ben Salah, R., Bozga, M., Maler, O.: Automatic Abstraction of Timed Components (submitted, 2006)Google Scholar
  5. [BGM02]
    Bozga, M., Graf, S., Mounier, L.: IF-2.0: A Validation Environment for Component-Based Real-Time Systems. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 343–348. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  6. [DGKK98]
    Dams, D., Gerth, R., Knaack, B., Kuiper, R.: Partial-order Reduction Techniques for Real-time Model Checking. Formal Aspects of Computing 10, 469–482 (1998)CrossRefMATHGoogle Scholar
  7. [DT98]
    Daws, C., Tripakis, S.: Model Checking of Real-Time Reachability Properties Using Abstractions. In: Steffen, B. (ed.) TACAS 1998. LNCS, vol. 1384, pp. 313–329. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  8. [DY96]
    Daws, C., Yovine, S.: Reducing the Number of Clock Variables of Timed Automata. In: RTSS 1996, pp. 73–81 (1996)Google Scholar
  9. [DR95]
    Diekert, V., Rozenberg, G. (eds.): The Book of Traces. World Scientific, Singapore (1995)Google Scholar
  10. [HBL+03]
    Hendriks, M., Behrmann, G., Larsen, K., Niebert, P., Vaandrager, F.: Adding Symmetry Reduction to Uppaal. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, pp. 46–59. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  11. [HNSY94]
    Henzinger, T., Nicollin, X., Sifakis, J., Yovine, S.: Symbolic Model-checking for Real-time Systems. Information and Computation 111, 193–244 (1994)Google Scholar
  12. [LNZ05]
    Lugiez, D., Niebert, P., Zennou, S.: A Partial Order Semantics Approach to the Clock Explosion Problem of Timed Automata. Theoretical Computer Science 345, 27–59 (2005)CrossRefMathSciNetMATHGoogle Scholar
  13. [MP95]
    Maler, O., Pnueli, A.: Timing Analysis of Asynchronous Circuits using Timed Automata. In: Camurati, P.E., Eveking, H. (eds.) CHARME 1995. LNCS, vol. 987, pp. 189–205. Springer, Heidelberg (1995)Google Scholar
  14. [M99]
    Minea, M.: Partial Order Reduction for Model Checking of Timed Automata. In: Baeten, J.C.M., Mauw, S. (eds.) CONCUR 1999. LNCS, vol. 1664, pp. 431–446. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  15. [R94]
    Rokicki, T.G.: Representing and Modeling Digital Circuits. PhD Thesis, Stanford University (1994)Google Scholar
  16. [T98]
    Tripakis, S.: The Analysis of Timed Systems in Practice, PhD Thesis, Université Joseph Fourier, Grenoble (1998)Google Scholar
  17. [U]
  18. [YS97]
    Yoneda, T., Schlingloff, B.-H.: Efficient Verification of Parallel Real-Time Systems. Formal Methods in System Design, 11, 187–215 (1997)Google Scholar
  19. [ZYN03]
    Zennou, S., Yguel, M., Niebert, P.: ELSE: A New Symbolic State Generator for Timed Automata. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, pp. 273–280. Springer, Heidelberg (2004)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ramzi Ben Salah
    • 1
  • Marius Bozga
    • 1
  • Oded Maler
    • 1
  1. 1.VERIMAGGieresFrance

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