Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs

  • Doosan Cho
  • Ayyagari Ravi
  • Gang-Ryung Uh
  • Yunheung Paek
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4097)


An iterative modulo scheduling is very important for compilers targeting high performance multi-issue digital signal processors. This is because these processors are often severely limited by idle state functional units and thus the reduced idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as mac, usually increase data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler.

In this work, we propose a technique that efficiently reselects instructions of an application loop code considering dependence complexity, which directly resolve the dependence constraint. That is specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NP-hard problem that necessitates complex assignments of registers and functional units. Our technique uses a heuristic to efficiently handle this problem in pre-stage of iterative modulo scheduling without loop unrolling.


code generation and optimization application specific embedded software design software pipelining dependence analysis high performance DSPs 


  1. 1.
    Tiernan, J.: An efficient search algorithm to find the elementary circuits of a graph. Communications of the ACM, 12–35 (December 1970)Google Scholar
  2. 2.
    Smith, D.R.: Random trees and the analysis of branch and bound procedures. Journal of the Association for Computing Machinery (January 1984)Google Scholar
  3. 3.
    Lam, M.: Software pipelining: an effective scheduling technique for VLIW machines. In: Proceedings of the SIGPLAN 1988 Conference on Programming Language Design and Implementation (June 1988)Google Scholar
  4. 4.
    Huff, R.: Lifetime-Sensitive Modulo Scheduling. In: Proceedings of the SIGPLAN 1993 Conference on Programming Language Design and Implementation (June 1993)Google Scholar
  5. 5.
    Rau, B.: Iterative modulo scheduling. HP Laboratories Technical Report, HPL94115 (November 1995)Google Scholar
  6. 6.
    Tyson, G., Smelyanskiy, M., Davidson, E.: Evaluating the Use of Register Queues in Software Pipelined Loops. IEEE Transactions on Computers 50(8), 769–783 (2001)Google Scholar
  7. 7.
    Zhuge, Q., Xiao, B., Sha, E.: Code Size reduction technique and implementation for software-pipelined DSP applications. ACM Transactions on Embedded Computing Systems 2(4), 590–613 (2003)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Doosan Cho
    • 1
  • Ayyagari Ravi
    • 3
  • Gang-Ryung Uh
    • 3
  • Yunheung Paek
    • 1
    • 2
  1. 1.School of Electrical Engineering and Computer SciencesSeoul National UniversitySeoulKorea
  2. 2.Center for SoC Design Technology in Seoul National University 
  3. 3.Department of Computer ScienceBoise State UniversityUSA

Personalised recommendations