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A Processor Extension for Cycle-Accurate Real-Time Software

  • Nicholas Jun Hao Ip
  • Stephen A. Edwards
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4096)

Abstract

Certain hard real-time tasks demand precise timing of events, but the usual software solution of periodic interrupts driving a scheduler only provides precision in the millisecond range. NOP-insertion can provide higher precision, but is tedious to do manually, requires predictable instruction timing, and works best with simple algorithms.

To achieve high-precision timing in software, we propose instruction-level access to cycle-accurate timers. We add an instruction that waits for a timer to expire then reloads it synchronously. Among other things, this provides a way to exactly specify the period of a loop.

To validate our approach, we implemented a simple RISC processor with our extension on an FPGA and programmed it to behave like a video controller and an asynchronous serial receiver. Both applications were much easier to write and debug than their hardware counterparts, which took roughly four times as many lines in VHDL. Simple processors with our extension brings software-style development to a class of applications that were once only possible with hardware.

Keywords

Assembly Code Baud Rate WCET Analysis Simple Processor Front Porch 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Nicholas Jun Hao Ip
    • 1
  • Stephen A. Edwards
    • 1
  1. 1.Department of Computer ScienceColumbia University 

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