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Computer Assisted Source-Code Parallelisation

  • Peter J. Vidler
  • Michael J. Pont
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3984)

Abstract

Many single-processor embedded systems are implemented using a time-triggered co-operative (TTC) scheduler. When considering possible alternatives to such a design, one option is a multi-CPU architecture, created using off-the-shelf processors or SoC techniques. In order to allow the rapid assessment of such design alternatives, we are exploring ways in which single-processor TTC code may be “automatically” converted to a multi-CPU equivalent. In this paper, we discuss the design of a prototype source code conversion tool. The input to this tool is the source code for the tasks of a single processor system using a TTC scheduler. The output from the tool (in the current version) is the equivalent multi-processor code based on either a “domino” scheduler or a shared-clock scheduler. In order to assess the effectiveness of the tool, we have used it it in a non-trivial case study: the results from this study are presented in detail.

Keywords

Conversion Process Controller Area Network Dynamic Voltage Scaling Translation Unit Conversion Tool 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Peter J. Vidler
    • 1
  • Michael J. Pont
    • 1
  1. 1.Embedded Systems LaboratoryUniversity of LeicesterLEICESTERUK

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