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An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks

  • Dirk Koch
  • Thilo Streichert
  • Steffen Dittrich
  • Christian Strengert
  • Christian D. Haubelt
  • Jürgen Teich
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3894)

Abstract

Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system designers benefit from this new technology, powerful infrastructures and programming environments are needed. In this paper, we will propose new concepts of an operating system (OS) infrastructure for reconfigurable networks that allow to efficiently design fault-tolerant systems. For this purpose, we consider a hardware/software solution that supports dynamic rerouting, hardware and software task migration, hardware/software task morphing, and online partitioning. Finally, we will present an implementation of such a reconfigurable network providing this OS infrastructure.

Keywords

Fault Tolerance Faulty Node Data Transfer Rate Task Migration Reconfigurable Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Lysecky, R., Vahid, F.: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. In: Proceedings of the Conference on Design, Automation and Test in Europe, Paris, France, pp. 480–485 (2004)Google Scholar
  2. 2.
    Streichert, T., Haubelt, C., Teich, J.: Online HW/SW-Partitioning in Networked Embedded Systems. In: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp. 982–985 (2005)Google Scholar
  3. 3.
    Walder, H., Platzner, M.: Online Scheduling for Block-partitioned Reconfigurable Devices. In: Proc. of Design, Automation and Test in Europe (DATE 2003), pp. 290–295 (2003)Google Scholar
  4. 4.
    Ahmadinia, A., Bobda, C., Koch, D., Majer, M., Teich, J.: Task Scheduling for Heterogeneous Reconfigurable Computers. In: Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Pernambuco, Brazil, pp. 22–27 (2004)Google Scholar
  5. 5.
    Ahmadinia, A., Bobda, C., Teich, J.: On-line Placement for Dynamic Reconfigurable Devices. Int. Journal of Embedded Systems (IJES) (2005)Google Scholar
  6. 6.
    Hecht, R., Timmermann, D., Kubisch, S., Zeeb, E.: Network-on-Chip basierende Laufzeitsysteme für dynamisch rekonfigurierbare Hardware. In: Müller-Schloer, C., Ungerer, T., Bauer, B. (eds.) ARCS 2004. LNCS, vol. 2981, pp. 185–194. Springer, Heidelberg (2004)Google Scholar
  7. 7.
    Baumgarte, V., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: PACT XPP - A Self-Reconfigurable Data Processing Architecture. In: ERSA, Nevada (2001)Google Scholar
  8. 8.
    Chameleon Systems: CS2000 Reconfigurable Communications Processor, Family Product Brief (2000)Google Scholar
  9. 9.
    Thomas, A., Becker, J.: Aufbau- und Strukturkonzepte einer multigranularen rekonfigurierbaren Hardwarearchitektur. In: Müller-Schloer, C., Ungerer, T., Bauer, B. (eds.) ARCS 2004. LNCS, vol. 2981, pp. 165–174. Springer, Heidelberg (2004)Google Scholar
  10. 10.
    Bobda, C., Koch, D., Majer, M., Ahmadinia, A., Teich, J.: A Dynamic NoC Approach for Communication in Reconfigurable Devices. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 1032–1036. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  11. 11.
    Dumitraş, T., Kerner, S., Mărculescu, R.: Towards On-Chip Fault-Tolerant Communication. In: Proceedings of the Asia and South Pacific Design Automation Conference 2003, Kitakyushu, Japan (2003)Google Scholar
  12. 12.
    Elnozahy, E.N.M., Alvisi, L., Wang, Y.M., Johnson, D.: A Survey of Rollback-Recovery Protocols in Message-Passing Systems. ACM Comput. Surv. 34(3) (2002)Google Scholar
  13. 13.
    Streichert, T., Haubelt, C., Teich, J.: Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems. In: Proc. of DATE 2005, Munich, Germany (2005)Google Scholar
  14. 14.
    Cybenko, G.: Dynamic Load Balancing for Distributed Memory Multiprocessors. Journal of Parallel and Distributed Computing 7, 279–301 (1989)CrossRefGoogle Scholar
  15. 15.
    Altera: Nios Development Board - Reference Manual, Cyclone Edition (2005), http://www.altera.com
  16. 16.
    Altera: Nios II Processor Reference Handbook (2005)Google Scholar
  17. 17.
    Labrosse, J.: micro-C/OS-II. 2nd edn. (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Dirk Koch
    • 1
  • Thilo Streichert
    • 1
  • Steffen Dittrich
    • 1
  • Christian Strengert
    • 1
  • Christian D. Haubelt
    • 1
  • Jürgen Teich
    • 1
  1. 1.Department of Computer Science, 12University of Erlangen-NurembergGermany

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