Integrating a New Cluster Assignment and Scheduling Algorithm into an Experimental Retargetable Code Generation Framework

  • K. Vasanta Lakshmi
  • Deepak Sreedhar
  • Easwaran Raman
  • Priti Shankar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3769)


This paper presents a new unified algorithm for cluster assignment and region scheduling, and its integration into an experimental retargetable code generation framework. The components of the framework are an instruction selector generator based on a recent technique, the IMPACT front end, a machine description module which uses a modification of the HMDES machine description language to include cluster information, a combined cluster allocator and an acyclic region scheduler, and a register allocator. Experiments have been carried out on the targeting of the tool to the Texas Instruments TMS320c62x architecture. We report preliminary results on a set of TI benchmarks.


Turkey Trimaran 


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  1. 1.
    Shankar, P., Gantait, A., Yuvaraj, A.R., Madhavan, M.: A New Algorithm For Linear Regular Tree Pattern Matching. Theoretical Computer Science 242, 125–142 (2000)MATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Sreedhar, D., Easwaran, R.: Retargetable code generation for clustered embedded processors, ME Project Report. Dept of CSA, Indian Institute of ScienceGoogle Scholar
  3. 3.
    Chaitin, G.J.: Register Allocation and Spilling via Graph Coloring. In: Proceedings of the 1982 Symposium on Compiler Construction, June 1982, pp. 98–105 (1982)Google Scholar
  4. 4.
    Briggs, P., Cooper, K., Torczon, L.: Improvements to Graph Coloring Register Allocation. ACM Transactions on Programming Languages and Systems 16(3), 428–455 (1994)CrossRefGoogle Scholar
  5. 5.
    Proebsting, T.A., Fraser, C.W.: Detecting Pipeline Hazards Quickly. In: 21st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (January 1994)Google Scholar
  6. 6.
    Texas Instruments TMS320C6000 CPU and Instruction Set Reference GuideGoogle Scholar
  7. 7.
    Leupers, R.: Instruction Scheduling for Clustered VLIW DSPs. In: Proceedings of the International Conference on Parallel Architecture and Compilation Techniques, Philadelphia, PA (October 2000)Google Scholar
  8. 8.
    Hwu, W.-m.: The superblock: An effective structure for VLIW and superscalar compilation. The Journal of Supercomputing 7, 229–248 (1993)CrossRefGoogle Scholar
  9. 9.
    Aho, A.V., Ullman, J.D.: Principles of Compiler Design. Addison-Wesley, Reading (1977)Google Scholar
  10. 10.
    Kailas, K., Ebcioglu, K., Agrawala, A.: CARS: A New Code Generation Framework for Clustered ILP Processors. In: 7th Interbational SYmposium on High Performance Computer Architecture, pp. 133–143 (2001)Google Scholar
  11. 11.
    Madhavan, M., Shankar, P., Rai, S., Ramakrishna, U.: Extending Graham-Glanville techniques for optimal code generation. ACM Trans. Program. Lang. Syst. 22(6), 973–1001 (2000)CrossRefGoogle Scholar
  12. 12.
  13. 13.
    Lee, W., Puppin, D., Swenson, S., Amarasinghe, S.: Convergent Scheduling. In: MICRO-35, Istanbul, Turkey (November 2002)Google Scholar
  14. 14.
    Capitanio, A., Dutt, N., Nicolau, A.: Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeos. In: 25th International Symposium on Microarchitecture, MICRO (1992)Google Scholar
  15. 15.
    Ellis, J.R.: Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge (1986)Google Scholar
  16. 16.
    Kailas, K., Ebcioglu, K., Agrawala, A.K.: CARS: A New Code Generation Framework for Clustered ILP Processors. In: 7th International Symposium on High Performance Computer Architecture (HPCA)Google Scholar
  17. 17.
    Ozer, E., Banerjia, S., Conte, T.M.: Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. In: 31st International Symposium on Microarchitecture (MICRO)Google Scholar
  18. 18.
    Desoli, G.: Instruction Assignment for Clustered VLIW DSP Compilers: a New Approach. Technical Report HPL-98-13, Hewlett Packard Laboratories (1998)Google Scholar
  19. 19.
    The Impact Research Group, University of Urbana Champaign.,
  20. 20.
    Trimaran Compiler,

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • K. Vasanta Lakshmi
    • 1
  • Deepak Sreedhar
    • 1
  • Easwaran Raman
    • 1
  • Priti Shankar
    • 1
  1. 1.Computer Science & AutomationIndian Institute of ScienceBangaloreIndia

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