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A Low-Complexity Issue Queue Design with Speculative Pre-execution

  • Won W. Ro
  • Jean-Luc Gaudiot
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3769)

Abstract

Current superscalar architectures inherently depend on an instruction issue queue to achieve multiple instruction issue and out-of-order execution. However, the issue queue is implemented as a centralized structure and mainly causes globally broadcasting operations to wake up and select the instructions. Therefore, a large issue queue ultimately results in a low clock rate along with a high circuit complexity. This paper proposes Speculative Pre-Execution Assisted by compileR (SPEAR), a low-complexity issue queue design. SPEAR is designed to manage the small issue queue more efficiently without increasing the queue size. To this end, we have first recognized that the long memory latency is one of the factors which demand a large queue, and we aim at achieving early execution of the miss-causing load instructions using another hierarchy of an issue queue. We speculatively pre-execute those miss-causing instructions as an additional prefetching thread.

Keywords

Queue Size Load Instruction Main Thread Spear Approach Annual International Symposium 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Won W. Ro
    • 1
  • Jean-Luc Gaudiot
    • 2
  1. 1.Department of Electrical and Computer EngineeringCalifornia State UniversityNorthridge
  2. 2.Department of Electrical Engineering and Computer ScienceUniversity of CaliforniaIrvine

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