Separate Compilation for Synchronous Modules

  • Jia Zeng
  • Stephen A. Edwards
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3820)

Abstract

Synchronous models are useful for designing real-time embedded systems because they provide timing control and deterministic concurrency. However, the semantics of such models usually require an entire system to be compiled at once to analyze the dependencies among modules. The alternative is to write modules that can respond when the values of some of their inputs are unknown, a tedious and error-prone process.

We present a compilation technique that allows a programmer to describe synchronous modules without having to consider undefined inputs. Our algorithm transforms such a description into code that does as much as it can with undefined inputs, allowing modules to be compiled separately and assembled later.

We implemented our technique in a compiler for the Esterel language and present results that show the technique does not impose a substantial overhead.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Benveniste, A., Caspi, P., Edwards, S.A., Halbwachs, N., Guernic, P.L., de Simone, R.: The synchronous languages 12 years later. Proceedings of the IEEE 91, 64–83 (2003) (Invited)CrossRefGoogle Scholar
  2. 2.
    Berry, G., Bouali, A., Fornari, X., Ledinot, E., Nassor, E., De Simone, R.: Esterel: A formal method applied to avionic software development. Science of Computer Programming 36, 5–25 (2000)CrossRefGoogle Scholar
  3. 3.
    Arditi, L., Bouali, A., Boufaied, H., Clave, G., Hadj-Chaib, M., Leblanc, L., de Simone, R.: Using Esterel and formal methods to increase the confidence in the functional validation of a commercial DSP. In: Proceedings of the ERCIM Workshop on Formal Methods for Industrial Critical Systems (FMICS), Trento, Italy (1999)Google Scholar
  4. 4.
    Vachharajani, M., Vachharajani, N., August, D.I.: The Liberty structural specification language: A high-level modeling language for component reuse. In: Proceedings of the ACM SIGPLAN Conference on Program Language Design and Implementation, PLDI (2004)Google Scholar
  5. 5.
    Penry, D.A., August, D.I.: Optimizations for a simulator construction system supporting reusable components. In: Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 926–931 (2003)Google Scholar
  6. 6.
    Edwards, S.A., Lee, E.A.: The semantics and execution of a synchronous block-diagram language. Science of Computer Programming 48, 21–42 (2003)MATHMathSciNetGoogle Scholar
  7. 7.
    Buck, J.T., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: A mixed-paradigm simulation/prototyping platform in C++. In: Proceedings of the C++ At Work Conference, Santa Clara, California (1991)Google Scholar
  8. 8.
    Berry, G., Gonthier, G.: The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming 19, 87–152 (1992)MATHCrossRefGoogle Scholar
  9. 9.
    Bryant, R.E.: Binary decision diagrams and beyond: Enabling technologies for formal verification. In: Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, California, pp. 236–243 (1995)Google Scholar
  10. 10.
    Chiodo, M., Giusto, P., Jurecska, A., Lavagno, L., Hsieh, H., Suzuki, K., Sangiovanni-Vincentelli, A., Sentovich, E.: Synthesis of software programs for embedded control applications. In: Proceedings of the 32nd Design Automation Conference, pp. 587–592. Association for Computing Machinery, San Francisco (1995)CrossRefGoogle Scholar
  11. 11.
    Edwards, S.A.: Compiling concurrent languages for sequential processors. ACM Transactions on Design Automation of Electronic Systems 8, 141–187 (2003)CrossRefGoogle Scholar
  12. 12.
    Zeng, J., Soviani, C., Edwards, S.A.: Generating fast code from concurrent program dependence graphs. In: Proceedings of Languages, Compilers, and Tools for Embedded Systems (LCTES), Washington, DC, pp. 175–181 (2004)Google Scholar
  13. 13.
    Potop-Butucaru, D.: Optimizations for faster execution of Esterel programs. In: Proceedings of Memocode, Mont St. Michel, France, pp. 227–236 (2003)Google Scholar
  14. 14.
    Murgai, R., Hirose, F., Fujita, M.: Logic synthesis for a single large look-up table. In: International Workshop on Logic Synthesis, pp. 6–11–6–19 (1995)Google Scholar
  15. 15.
    Ashar, P., Malik, S.: Fast functional simulation using branching programs. In: Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, California, pp. 408–412 (1995)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Jia Zeng
    • 1
  • Stephen A. Edwards
    • 1
  1. 1.Department of Computer ScienceColumbia UniversityNew YorkUSA

Personalised recommendations