A Low-Power DSP-Enhanced 32-Bit EISC Processor

  • Hyun-Gyu Kim
  • Hyeong-Cheol Oh
Conference paper

DOI: 10.1007/11587514_20

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3793)
Cite this paper as:
Kim HG., Oh HC. (2005) A Low-Power DSP-Enhanced 32-Bit EISC Processor. In: Conte T., Navarro N., Hwu W.W., Valero M., Ungerer T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2005. Lecture Notes in Computer Science, vol 3793. Springer, Berlin, Heidelberg


EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications and has higher code density than its competing architectures. In this paper, we propose a low-power DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications while adding relatively low hardware overhead. Our simulation results show that the proposed DSP-enhanced processor reduces the execution time of the considered DSP kernels by 77.6% and the MP3 applications by 30.9%. The proposed DSP enhancements cost approximately 10300 gates (18%) and do not increase the clock frequency. While the high code density of EISC would be of great advantage to a low-power embedded system, the proposed DSP enhancement could increase its power consumption by 16.9%. We show that a set of supports for power management could reduce the power consumption by 65.5%. The proposed processor has been embedded in an SoC for video processing and proven in silicon.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Hyun-Gyu Kim
    • 1
    • 2
  • Hyeong-Cheol Oh
    • 3
  1. 1.Dept. of Elec. and Info. Eng.Graduate School, Korea Univ.SeoulKorea
  2. 2.Advanced Digital ChipsR&D centerSeoulKorea
  3. 3.Dept. of Info. Eng.Korea Univ. at Seo-ChangChung-NamKorea

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