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Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs

  • Eun-Gu Jung
  • Eon-Pyo Hong
  • Kyoung-Son Jhang
  • Jeong-A Lee
  • Dong-Soo Har
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3767)

Abstract

In this paper, a high performance asynchronous on-chip bus designed in a Globally Asynchronous Locally Synchronous (GALS) style is proposed. The asynchronous on-chip bus is capable of handling multiple outstanding transactions and in-order completion to achieve a high performance, which is implemented with distributed and modularized control unit in a layered interface. The architecture of asynchronous on-chip bus is discussed and implemented for simulations. Simulation results show that throughput of the proposed asynchronous on-chip bus with multiple outstanding transactions and in-order transaction completion is increased by 31.3%, while power consumption overhead is only 6.76%, as compared to an asynchronous on-chip bus with a single outstanding transaction.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Eun-Gu Jung
    • 1
  • Eon-Pyo Hong
    • 1
  • Kyoung-Son Jhang
    • 2
  • Jeong-A Lee
    • 3
  • Dong-Soo Har
    • 1
  1. 1.Department of Information and CommunicationsGwangju Institute of Science and TechnologyRepublic of Korea
  2. 2.Department of Computer Engineering, College of EngineeringChungnam National UniversityRepublic of Korea
  3. 3.Department of Computer EngineeringChosun UniversityRepublic of Korea

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