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Improving Latency Tolerance of Network Processors Through Simultaneous Multithreading

  • Bo Liang
  • Hong An
  • Fang Lu
  • Rui Guo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3756)

Abstract

Existing multithreaded network processors architecture with multiple processing engines (PEs), aims at taking advantage of blocked multithreading technique which executes instructions of different user-defined threads in the same PE pipeline, in explicit and interleave way. Multiple PEs, each of which is a multithreaded processor core, process several packets in parallel to hide long memory access latency. Most of them are optimized for throughputs mostly in data-plane. In future network workloads, the boundaries between data-plane and control-plane become blurred, so that PEs are demanded not only wire speed packet forwarding on data-plane, but also highly intelligent and increased complex packet processing function on control-plane. In this paper, we analyze SMT’s short latency tolerance potential when used in out-of-order and dynamic scheduling PE cores. We show in this paper that 2~4 issue SMT provides an excellent short memory and branch latency tolerance, which gain higher instructions throughout as well as much simpler structures.

Keywords

Branch Latency Benchmark Suite Network Address Translation Network Processor Branch Prediction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Bo Liang
    • 1
  • Hong An
    • 1
    • 2
  • Fang Lu
    • 1
  • Rui Guo
    • 1
  1. 1.Department of Computer Science and TechnologyUniversity of Science and Technology of ChinaHefeiChina
  2. 2.Computer Architecture Laboratory, Institute of Computing TechnologyChinese Academy of SciencesBeijingChina

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