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A New Reachability Algorithm for Symmetric Multi-processor Architecture

  • Debashis Sahoo
  • Jawahar Jain
  • Subramanian Iyer
  • David Dill
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3707)

Abstract

Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. A naive parallelization of such algorithms is often ineffective as they have less parallelism. In this paper we present a novel parallel reachability approach that lead to a significantly faster verification on a Symmetric Multi-Processing architecture over the existing one-thread, one-CPU approaches. We identify the issues and bottlenecks in parallelizing BDD-based reachability algorithm. We show that in most cases our algorithm achieves good speedup compared to the existing sequential approaches.

Keywords

Reachability Analysis Early Communication Partial Communication Order Binary Decision Diagram Idle Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Clarke, E., Emerson, E.: Design and synthesis of synchronization skeletons using branching time temporal logic. In: Logic of Programs 1981. LNCS, vol. 131. Springer, Heidelberg (1981)Google Scholar
  2. 2.
    McMillan, K.L.: Symbolic Model Checking. Kluwer Academic Publishers, Dordrecht (1993)zbMATHGoogle Scholar
  3. 3.
    Bryant, R.: Graph-based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers C-35, 677–691 (1986)CrossRefGoogle Scholar
  4. 4.
    Coudert, O., Berthet, C., Madre, J.C.: Verification of sequential machines based on symbolic execution. In: Proc. of the Workshop on Automatic Verification Methods for Finite State Systems (1989)Google Scholar
  5. 5.
    Jain, J., et al.: Functional Partitioning for Verification and Related Problems. In: Brown/MIT VLSI Conference (1992)Google Scholar
  6. 6.
    Narayan, A., et al.: Reachability Analysis Using Partitioned-ROBDDs. In: ICCAD, pp. 388–393 (1997)Google Scholar
  7. 7.
    Iyer, S., Sahoo, D., Stangier, C., Narayan, A., Jain, J.: Improved symbolic Verification Using Partitioning Techniques. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 410–424. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  8. 8.
    Sahoo, D., Iyer, S., et al.: A Partitioning Methodology for BDD-based Verification. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol. 3312, pp. 399–413. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  9. 9.
    Stern, U., Dill, D.L.: Parallelizing the murphy verifier. In: CAV (1997)Google Scholar
  10. 10.
    Stornetta, T., Brewer, F.: Implementation of an efficient parallel BDD package. In: DAC, pp. 641–644 (1996)Google Scholar
  11. 11.
    Garavel, H., Mateescu, R., Smarandache, I.: Parallel state space construction for model-checking. In: Dwyer, M.B. (ed.) SPIN 2001. LNCS, vol. 2057, pp. 217–234. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  12. 12.
    Heyman, T., Geist, D., Grumberg, O., Schuster, A.: Achieving scalability in parallel reachability analysis of very large circuits. In: CAV (2000)Google Scholar
  13. 13.
    Yang, B., O’Hallaron, D.R.: Parallel breadth-first bdd construction. In: Symposium on Principles and practice of parallel programming, pp. 145–156. ACM Press, New York (1997)CrossRefGoogle Scholar
  14. 14.
    Cabodi, G., Camurati, P., Lavagno, L., Quer, S.: Disjunctive partitioning and partial iterative squaring: An effective approach for symbolic traversal of large circuits. In: DAC, pp. 728–733 (1997)Google Scholar
  15. 15.
    Pixley, C., Havlicek, J.: A verification synergy: Constraint-based verification. In: Electronic Design Processes (2003)Google Scholar
  16. 16.
    Sahoo, D., Jain, J., Iyer, S.K., Dill, D.L., Emerson, E.A.: Multi-threaded reachability. In: DAC (2005) (to appear)Google Scholar
  17. 17.
    Ravi, K., Somenzi, F.: High-density reachability analysis. In: ICCAD, pp. 154–158 (1995)Google Scholar
  18. 18.
    Somenzi, F.: CUDD: CU Decision Diagram Package (2001), ftp://vlsi.colorado.edu/pub
  19. 19.
    VIS: Verilog Benchmarks (2001), http://vlsi.colorado.edu/~vis/

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Debashis Sahoo
    • 1
  • Jawahar Jain
    • 3
  • Subramanian Iyer
    • 2
  • David Dill
    • 1
  1. 1.Stanford UniversityStanfordUSA
  2. 2.University of Texas at AustinAustinUSA
  3. 3.Fujitsu Labs of America 

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