The Optimal Wire Order for Low Power CMOS

  • Paul Zuber
  • Peter Gritzmann
  • Michael Ritter
  • Walter Stechele
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3728)

Abstract

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.

Keywords

Power Saving Great Element Switching Activity Geometric Program Optimization Potential 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Paul Zuber
    • 1
  • Peter Gritzmann
    • 2
  • Michael Ritter
    • 2
  • Walter Stechele
    • 1
  1. 1.Institute for Integrated SystemsTU MünchenGermany
  2. 2.Institute for Combinatorial GeometryTU MünchenGermany

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