Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers

  • Daniel González
  • Luis Parrilla
  • Antonio García
  • Encarnación Castillo
  • Antonio Lloris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3728)

Abstract

Clock distribution has become an increasingly challenging problem for VLSI designs because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. Additionally, the great amount of synchronous hardware in integrated circuits makes current requirements to be very large at very precise instants. This paper presents a new approach for clock distribution in PID controllers based on RNS, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. The resulting VLSI RNS-enabled PID controller, shows a significant decrease in current requirements (the maximum current spike is reduced to a 14% of single clock distribution one at 125 Mhz) and a homogeneous time distribution of current supply to the chip, while keeping extra hardware and power to a minimum.

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References

  1. 1.
    Aström, K.J., Hägglund, T.: PID Control. Theory, Design and Tunning, 2ended., Instrument Society of America. Research Triangle Par., NC (1995)Google Scholar
  2. 2.
    Szabo, N.S., Tanaka, R.I.: Residue Arithmetic and Its Applications to Computer Technology. McGraw-Hill, New York (1967)MATHGoogle Scholar
  3. 3.
    Parrilla, L., García, A., Lloris, A.: Implementation of High Performance PID Controllers using RNS and Field-Programmable Devices. In: Proc. of 2000 IFAC Workshop on Digital Control PID 2000, Terrassa, April 5-7, pp. 628–631 (2000)Google Scholar
  4. 4.
    Yuan, J., Svensson, C.: High-speed CMOS Circuit Technique. IEEE Journal of Solid State Circuits 24(1), 62–70 (1989)CrossRefGoogle Scholar
  5. 5.
    Bailey, D.W., Benchsneider, B.J.: Clocking Design and Analysis for a 600-MHz Alpha Microprocessor. IEEE Journal of Solid State Circuits 33, 1627–1633 (1998)CrossRefGoogle Scholar
  6. 6.
    Ramanathan, P., Dupont, A.J., Shin, K.G.: Clock Distribution in General VLSI Circuits. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41(5), 395–404 (1994)CrossRefGoogle Scholar
  7. 7.
    Yoo, J., Gopalakrishnan, G., Smith, K.F.: Timing Constraints for High-speed Counterflowclocked Pipelining. IEEE Transactions on VLSI Systems 7(2), 167–173 (1999)CrossRefGoogle Scholar
  8. 8.
    Grover, W.D.: A New Method for Clock Distribution. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41(2), 149–160 (1994)CrossRefGoogle Scholar
  9. 9.
    Jackson, M.A.B., Srinivasan, A., Kuh, E.S.: Clock Routing for High Performance IC.s. In: 27th ACM/IEEE Design Automation Conference (1990)Google Scholar
  10. 10.
    Wann, D.F., Franklin, N.A.: Asynchronous and Clocked Control Structures for VLSI Based Interconnect Networks. IEEE Transactions on Computers 32(5), 284–293 (1983)CrossRefGoogle Scholar
  11. 11.
    Hatamian, M.: Chapter 6, Understanding clock skew in synchronous systems. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds.) Concurrent Computations (Algorithms, Architecture, and Technology), pp. 87–96. Plenum Publishing, New York (1988)Google Scholar
  12. 12.
    Friedman, E.G.: Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proceedings of the IEEE 89(5) (2001)Google Scholar
  13. 13.
    Friedman, E.G., Powell, S.: Design and Analysis of an Hierarchical Clock Distribution System for Synchronous Cell/macrocell VLSI. IEEE Journal of Solid State Circuits 21(2), 240–246 (1986)CrossRefGoogle Scholar
  14. 14.
    Shoji, M.: Elimination of Process-dependent Clock skew in CMOS VLSI. IEEE Journal of Solid State Circuits 21, 869–880 (1986)CrossRefGoogle Scholar
  15. 15.
    Soderstrand, M.A., Jenkins, W.K., Jullien, G.A., Taylor, F.J.: Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, Los Alamitos (1986)MATHGoogle Scholar
  16. 16.
    MOSIS Process Information: Hewlett Packard AMOS14TB, http://www.mosis.org/technical/processes/proc-hp-amos14tb.html

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Daniel González
    • 1
  • Luis Parrilla
    • 1
  • Antonio García
    • 1
  • Encarnación Castillo
    • 1
  • Antonio Lloris
    • 1
  1. 1.Departament of Electronics and Computers TechnologyUniversity of GranadaGranadaSpain

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