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Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications

  • Flavio Carbognani
  • Felix Bürgin
  • Norbert Felber
  • Hubert Kaeslin
  • Wolfgang Fichtner
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3728)

Abstract

The energy efficiency of a 0.25 μm general-purpose FIR filter design, based on two-phase clocking, versus a functionally equivalent benchmark, based on one-phase clocking, is demonstrated by means of measurements and transistor level simulations. Architectural improvements enable already a 20% energy savings of the two-phase clocking implementation. Yet, for the first time, the limitations imposed by the supply voltage (< 2.1 V) and the operating frequency (< 10 MHz) on the actual energy efficiency of this low-power strategy are investigated. Transistor level re-design is undertaken: a new slew-insensitive latch is presented and replaced inside the two-phase implementation. Spectre simulations point out the final 30% savings.

Keywords

Supply Voltage Delay Cell Clock Tree Transistor Level Clock Gating 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Flavio Carbognani
    • 1
  • Felix Bürgin
    • 1
  • Norbert Felber
    • 1
  • Hubert Kaeslin
    • 1
  • Wolfgang Fichtner
    • 1
  1. 1.ETHZurichSwitzerland

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