Design Verification for Product Line Development

  • Tomoji Kishi
  • Natsuko Noda
  • Takuya Katayama
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3714)


Our society is becoming increasingly dependent on embedded software, and its reliability becomes more and more important. Although we can utilize powerful scientific methods such as model checking techniques to develop reliable embedded software, it is expensive to apply these methods to consumer embedded software development. In this paper, we propose an application of model checking techniques for design verification in product line development (PLD). We introduce reusable verification models in which we define variation points, and we show how to define traceability among feature models, design models and verification models. The reuse of verification models in PLD not only enables the systematic design verification of each product but also reduces the cost of applying model checking techniques.


Model Check Design Model Event Sequence Environment Model Product Family 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Tomoji Kishi
    • 1
  • Natsuko Noda
    • 2
  • Takuya Katayama
    • 1
  1. 1.School of Information ScienceJAIST-Japan Advanced Institute of Science and TechnologyIshikawaJapan
  2. 2.NEC CorporationTokyoJapan

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