AES on FPGA from the Fastest to the Smallest

  • Tim Good
  • Mohammed Benaissa
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3659)


Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3S2000) device. The second is believed to be the smallest and fits into a Xilinx Spartan-II (XC2S15) device, only requiring two block memories and 124 slices to achieve a throughput of 2.2 Mbps. These designs show the extremes of what is possible and have radically different applications from high performance e-commerce IPsec servers to low power mobile and home applications. The high speed design presented here includes support for continued throughput during key changes for both encryption and decryption which previous pipelined designs have omitted.


Advanced Encryption Standard (AES) Field Programmable Gate Array (FPGA) finite field design exploration high throughput pipelined low area Application Specific Instruction Processor (ASIP) 


  1. 1.
    National Institute of Standards and Technology (NIST), Information Technology Laboratory (ITL), Advanced Encryption Standard (AES), Federal Information Processing Standards (FIPS) Publication 197 (November 2001)Google Scholar
  2. 2.
    Zhang, X., Parhi, K.K.: High-speed VLSI architectures for the AES algorithm. IEEE Trans. VLSI Systems 12(9), 957–967 (2004)CrossRefGoogle Scholar
  3. 3.
    Hodjat, A., Verbauwhede, I.: A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. In: 12th Annual IEEE Sypmosium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 308–309 (April 2004)Google Scholar
  4. 4.
    Chodowiec, P., Gaj, K.: Very Compact FPGA Implementation of the AES Algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319–333. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  5. 5.
    Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.D.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: Procedings of the international conference on Information Technology: Coding and Computing 2004 (ITCC 2004), vol. 2, pp. 583–587 (April 2004)Google Scholar
  6. 6.
    Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong Authentication for RFID Systems Using the AES Algorithm. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 357–370. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  7. 7.
    Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  8. 8.
    Zambreno, J., Nguyen, D., Choudhary, A.: Exploring Area/Delay Trade-offs in an AES FPGA Implementation. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 575–585. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  9. 9.
    Jarvinen, K.U., Tommiska, M.T., Skytta, J.O.: A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In: Proc. Int. Symp. Field-Programmable Gate Arrays (FPGA 2003), Monterey, CA, pp. 207–215 (February 2003)Google Scholar
  10. 10.
    Saggese, G.P., Mazzeo, A., Mazocca, N., Strollo, A.G.M.: An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  11. 11.
    Standaert, F., Rouvroy, G., Quisquater, J., Legat, J.: Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements & design tradeoffs. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 334–350. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  12. 12.
    McLoone, M., McCanny, J.V.: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, p. 65. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  13. 13.
    Pramstaller, N., Wolkerstorfer, J.: A Universal and efficient AES co-processor for Field Programmable Logic Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 565–574. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  14. 14.
    Chapman, K.: PicoBlaze 8-bit Microcontroller. Xilinx (2002),

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Tim Good
    • 1
  • Mohammed Benaissa
    • 1
  1. 1.Department of Electronic & Electrical EngineeringUniversity of SheffieldSheffieldUK

Personalised recommendations