Comprehensive Cache Inspection with Hardware Monitors
Computer systems usually rely on hardware counters and software instrumentation to acquire performance information about the cache access behavior. These approaches either provide only limited data or are restricted in their applicability. This paper introduces a novel approach based on a hardware cache monitoring facility that exhibits both the details of traditional software mechanisms and the low–overhead of hardware counters. More specially, the cache monitor can be combined with any location of the memory hierarchy and present a detailed view of the complete memory access behavior of applications. The monitoring concept has been verified using a multiprocessor simulator. Initial experimental results show its feasibility in terms of hardware design and functionality with respect to providing comprehensive performance data.
Unable to display preview. Download preview PDF.
- 3.Digital Equipment Cooperation. Alpha 21164 Microprocessor Hardware Reference Manual. Technical report (1995)Google Scholar
- 4.Ghosh, S., Martonosi, M., Malik, S.: Automated Cache Optimizations using CME Driven Diagnosis. In: Proceedings of the 2000 International Conference on Supercomputing, pp. 316–326 (2000)Google Scholar
- 5.Intel Corporation. Intel Itanium Architecture Software Developer’s Manual, vol. 1–3 (2002), Available at http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm
- 6.Intel Corporation. IA-32 Intel Architecture Software Developer’s Manual, vol. 1–3 (2004), Available at Intel’s developer websiteGoogle Scholar
- 7.Magnusson, P.S., Werner, B.: Efficient Memory Simulation in SimICS. In: Proceedings of the 8th Annual Simulation Symposium, Phoenix, Arizona, USA (April 1995)Google Scholar
- 9.Martonosi, M., Gupta, A., Anderson, T.E.: Tuning Memory Performance in Sequential and Parallel Programs. IEEE Computer, 32–40 (April 1995)Google Scholar
- 10.Sun Microsystems. UltraSPARC IIi User’s Manual (October 1997), Available at http://www.sun.com/processors/documentation.html
- 11.Tao, J., Schulz, M., Karl, W.: A Simulation Tool for Evaluating Shared Memory Systems. In: Proceedings of the 36th Annual Simulation Symposium, Orlando, Florida, April 2003, pp. 335–342 (2003)Google Scholar
- 12.Welbon, E., et al.: The POWER2 Performance Monitor. IBM Journal of Research and Development 38(5) (1994)Google Scholar
- 13.Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 Programs: Characterization and Methodological Considerations. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995, pp. 24–36 (1995)Google Scholar