Trimaran: An Infrastructure for Research in Instruction-Level Parallelism

  • Lakshmi N. Chakrapani
  • John Gyllenhaal
  • Wen-mei W. Hwu
  • Scott A. Mahlke
  • Krishna V. Palem
  • Rodric M. Rabbah
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3602)


Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor architecture supporting novel features such as predication, control and data speculation and compiler controlled management of the memory hierarchy. Trimaran also consists of a full suite of analysis and optimization modules, as well as a graph-based intermediate language. Optimizations and analysis modules can be easily added, deleted or bypassed, thus facilitating compiler optimization research. Similarly, computer architecture research can be conducted by varying the HPL-PD machine via the machine description language HMDES. Trimaran also provides a detailed simulation environment and a flexible performance monitoring environment that automatically tracks the machine as it is varied.


Memory Hierarchy Intermediate Representation Design Space Exploration Register Allocation Software Pipeline 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Lakshmi N. Chakrapani
    • 1
  • John Gyllenhaal
    • 2
  • Wen-mei W. Hwu
    • 3
  • Scott A. Mahlke
    • 4
  • Krishna V. Palem
    • 1
  • Rodric M. Rabbah
    • 5
  1. 1.Georgia Institute of Technology 
  2. 2.Lawrence Livermore National Laboratory 
  3. 3.University of IllinoisUrbana-Champaign
  4. 4.University of Michigan 
  5. 5.Massachusetts Institute of Technology 

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