Power-Aware Scheduling for Parallel Security Processors with Analytical Models

  • Yung-Chia Lin
  • Yi-Ping You
  • Chung-Wen Huang
  • Jenq-Kuen Lee
  • Wei-Kuan Shih
  • Ting-Ting Hwang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3602)

Abstract

Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multiple-domain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogeneous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources that are of correlations. Experiments are done in the prototypical environments for our security processors and the results show that significant energy reductions can be achieved by our algorithms.

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References

  1. 1.
    Weiser, M., Welch, B., Demers, A., Shenker, S.: Scheduling for reduced cpu energy. In: Proceedings of USENIX Symposium on Operating Systems Design and Implementation (OSDI), pp. 13–23 (1994)Google Scholar
  2. 2.
    Butts, J.A., Sohi, G.S.: A static power model for architects. In: Proc. Int. Symp. on Microarchitecture, pp. 191–201 (2000)Google Scholar
  3. 3.
    Powell, M.D., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-vdd:a circuit technique to reduce leakage in deep-submicron cache memories. In: Proc. ISLPED (2000)Google Scholar
  4. 4.
    Hong, I., Kirovski, D., Qu, G., Potkonjak, M., Srivastava, M.B.: Power optimization of variable-voltage core-based systems. IEEE Trans. Computer-Aided Design 18, 1702–1714 (1999)CrossRefGoogle Scholar
  5. 5.
    Yao, F., Demers, A., Shenker, S.: A scheduling model for reduced cpu energy. In: Symp. Foundations of Computer Science, pp. 374–382 (1995)Google Scholar
  6. 6.
    Quan, G., Hu, X.: Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors. In: Proc. DAC, pp. 828–833 (2001)Google Scholar
  7. 7.
    Pouwelse, J., Langendoen, K., Sips, H.: Energy priority scheduling for variable voltage processors. In: Proc. ISLPED (2001)Google Scholar
  8. 8.
    Shin, Y., Choi, K.: Power conscious fixed priority scheduling for hard real-time systems. In: Proc. DAC, pp. 134–139 (1999)Google Scholar
  9. 9.
    Pering, T., Burd, T., Brodersen, R.: The simulation and evaluation of dynamic voltage scaling algorithms. In: Proc. ISLPED, pp. 76–81 (1998)Google Scholar
  10. 10.
    Krishna, C.M., Lee, L.H.: Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems. In: Proc. Real Time Technology and Applications Symp. (2000)Google Scholar
  11. 11.
    Ishihara, T., Yasuura, H.: Voltage scheduling problem for dynamically variable voltage processors. In: Proc. ISLPED, pp. 197–202 (1998)Google Scholar
  12. 12.
    Gruian, F., Kuchcinski, K.: Lenes: Task scheduling for low-energy systems using variable supply voltage processor. In: Proc. ASPDAC, pp. 449–455 (2001)Google Scholar
  13. 13.
    Manzak, A., Chakrabarti, C.: Variable voltage task scheduling for minimizing energy or minimizing power. In: Proc. ICASSP, pp. 3239–3242 (2000)Google Scholar
  14. 14.
    You, Y.P., Lee, C.R., Lee, J.K.: Real-time task scheduling for dynamically variable voltage processors. In: Proc. IEEE Workshop on Power Management for Real-Time and Embedded Systems (2001)Google Scholar
  15. 15.
    Lee, C.R., Lee, J.K., Hwang, T.T., Tsai, S.C.: Compiler optimizations on vliw instruction scheduling for low power. ACM Transactions on Design Automation of Electronic Systems 8, 252–268 (2003)CrossRefGoogle Scholar
  16. 16.
    Luo, J., Jha, N.K.: Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems. In: Proc. ICCAD, pp. 357–364 (2000)Google Scholar
  17. 17.
    Luo, J., Jha, N.K.: Battery-aware static scheduling for distributed real-time embedded systems. In: Proc. DAC, pp. 444–449 (2001)Google Scholar
  18. 18.
    Schmitz, M.T., Al-Hashimi, B.M.: Considering power variations of dvs processing elements for energy minimisation in distributed systems. In: Proc. ISSS, pp. 250–255 (2001)Google Scholar
  19. 19.
    Luo, J., Jha, N.: Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems. In: Proc. ASPDAC (2002)Google Scholar
  20. 20.
    You, Y.P., Lee, C.R., Lee, J.K.: Compiler analysis and support for leakage power reduction on microprocessors. In: Pugh, B., Tseng, C.-W. (eds.) LCPC 2002. LNCS, vol. 2481, pp. 45–60. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  21. 21.
    Duarte, D., Tsai, Y., Vijaykrishnan, N., Irwin, M.J.: Evaluating run-time techniques for leakage power reduction. In: Proc. ASPDAC (2002)Google Scholar
  22. 22.
    Rele, S., Pande, S., Onder, S., Gupta, R.: Optimizing static power dissipation by functional units in superscalar processors. In: Proc. Int. Conf. on Compiler Construction, pp. 261–275 (2002)Google Scholar
  23. 23.
    Su, C.Y., Hwang, S.A., Chen, P.S., Wu, C.W.: An improved montgomery algorithm for high-speed rsa public-key cryptos ystem. IEEE Transactions on VLSI Systems 7, 280–284 (1999)CrossRefGoogle Scholar
  24. 24.
    Hong, J.H., Wu, C.W.: Cellular array modular multiplier for the rsa public-key cryptosystem based on modified booth’s algorithm. IEEE Transactions on VLSI Systems 11, 474–484 (2003)CrossRefGoogle Scholar
  25. 25.
    Lin, T.F., Su, C.P., Huang, C.T., Wu, C.W.: A high-throughput low-cost aes cipher chip. In: 3rd IEEE Asia-Pacific Conf. ASIC (2002)Google Scholar
  26. 26.
    Su, C.P., Lin, T.F., Huang, C.T., Wu, C.W.: A highly efficient aes cipher chip. In: ASP-DAC (2003)Google Scholar
  27. 27.
    Wang, M.Y., Su, C.P., Huang, C.T., Wu, C.W.: An hmac processor with integrated sha-1 and md5 algorithms. In: ASP-DAC (2004)Google Scholar
  28. 28.
    Lee, M.C., Huang, J.R., Su, C.P., Chang, T.Y., Huang, C.T., Wu, C.W.: A true random generator desing. In: 13th VLSI Design/CAD Symp. (2002)Google Scholar
  29. 29.
    Hifn: 7954 security processor Data Sheet (2003)Google Scholar
  30. 30.
    Gammage, N., Waters, G.: Securing the Smart Network with Motorola Security Processors (2003)Google Scholar
  31. 31.
    Stankovic, J.A., Spuri, M., Natale, M.D., Buttazzo, G.: Implications of Classical Scheduling Results For Real-Time Systems., vol. 28 (1995)Google Scholar
  32. 32.
    Shih, W.K., Liu, J.W.S.: On-line scheduling of imprecise computations to minimize error. SIAM Journal on Computing 25, 1105–1121 (1996)MATHCrossRefMathSciNetGoogle Scholar
  33. 33.
    Liu, C.L., Layland, J.W.: Scheduling algorithms for multiprogramming in a hard read-time environment. Journal of the ACM 20, 46–61 (1973)MATHCrossRefMathSciNetGoogle Scholar
  34. 34.
    Lapin, L.L.: Modern Engineering Statistics. Wadsworth Publishing Company, WBelmont (1997)Google Scholar
  35. 35.
    Chen, R.Y., Irwin, M.J.: Architecture-level power estimation and design experiments. ACM Transactions on Design Automation of Electronic Systems 6, 50–66 (2001)CrossRefGoogle Scholar
  36. 36.
    Doyle, B., Arghavani, R., Barlage, D., Datta, S., Doczy, M., Kavalieros, J., Murthy, A., Chau, R.: Transistor elements for 30nm physical gate lengths and beyond. Intel Technology Journal 6, 42–54 (2002)Google Scholar
  37. 37.
    Hwang, K., Briggs, F.: Computer Architecture and Parallel Processing. McGraw-Hill, New York (1984)MATHGoogle Scholar
  38. 38.
    Bodin, F., Windheiser, D., Jalby, W., Atapattu, D., Lee, M., Gannon, D.: Performance evaluation and prediction for parallel algorithms on the bbn gp1000. In: Proc. of the 4th ACM International Conference on Supercomputing, pp. 401–403 (1990)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Yung-Chia Lin
    • 1
  • Yi-Ping You
    • 1
  • Chung-Wen Huang
    • 1
  • Jenq-Kuen Lee
    • 1
  • Wei-Kuan Shih
    • 1
  • Ting-Ting Hwang
    • 1
  1. 1.National Tsing Hua UniversityHsinchu 300Taiwan

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