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F-Soft: Software Verification Platform

  • F. Ivančić
  • Z. Yang
  • M. K. Ganai
  • A. Gupta
  • I. Shlyakhter
  • P. Ashar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3576)

Abstract

In this paper, we describe our verification tool F-Soft, which is developed for the analysis of C programs. Its novelty lies in the combination of several recent advances in formal verification research including SAT-based verification, static analyses and predicate abstraction. As shown in the tool overview in Figure 1, we translate a program into a Boolean model to be analyzed by our verification engine DiVer [4], which includes BDD-based and SAT-based model checking techniques. We include various static analyses, such as computing the control flow graph of the program, program slicing with respect to the property, and performing range analysis as described in Section 2.2. We model the software using a Boolean representation, and use customized heuristics for the SAT-based analysis as described in Section [2.1]. We can also perform a localized predicate abstraction with register sharing as described in Section [2.3], if the user so chooses. The actual analysis of the resulting Boolean model is performed using DiVer. If a counter-example is discovered, we use a testbench generator that automatically generates an executable program for the user to examine the bug in his/her favorite debugger. The F-Soft tool has been applied on numerous case studies and publicly available benchmarks for sequential C programs. We are currently working on extending it to handle concurrent programs.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • F. Ivančić
    • 1
  • Z. Yang
    • 1
  • M. K. Ganai
    • 1
  • A. Gupta
    • 1
  • I. Shlyakhter
    • 1
  • P. Ashar
    • 1
  1. 1.NEC Laboratories AmericaPrincetonUSA

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