Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures

  • Stefan Farfeleder
  • Andreas Krall
  • Nigel Horspool
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3553)


Emulation of one architecture on another is useful when the architecture is under design, when software must be ported to a new platform or is being developed for systems which are still under development, or for embedded systems that have insufficient resources to support the software development process. Emulation using an interpreter is typically slower than normal execution by up to 3 orders of magnitude. Our approach instead translates the program from the original architecture to another architecture while faithfully preserving its semantics at the lowest level. The emulation speeds are comparable to, and often faster than, programs running on the original architecture. Partial evaluation of architectural features is used to achieve such impressive performance, while permitting accurate statistics collection. Accuracy is at the level of the number of clock cycles spent executing each instruction (hence the description cycle-accurate).


Basic Block Digital Signal Processor Single Instruction Multiple Data Program Counter Loop Body 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Stefan Farfeleder
    • 1
  • Andreas Krall
    • 1
  • Nigel Horspool
    • 2
  1. 1.Institut für ComputersprachenTU WienAustria
  2. 2.Department of Computer ScienceUniversity of VictoriaCanada

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