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FPGA Logic Synthesis Using Quantified Boolean Satisfiability

  • Andrew Ling
  • Deshanand P. Singh
  • Stephen D. Brown
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3569)

Abstract

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The applications demonstrated in this paper include FPGA technology mapping and resynthesis where their results show significant FPGA performance improvements.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Andrew Ling
    • 1
  • Deshanand P. Singh
    • 2
  • Stephen D. Brown
    • 2
  1. 1.University of TorontoTorontoCanada
  2. 2.Toronto Technology CentreAltera CorporationTorontoCanada

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