Determinate STG Decomposition of Marked Graphs

  • Mark Schäfer
  • Walter Vogler
  • Petr Jančar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3536)


STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. To find the best possible result the algorithm might produce, it would be important to know to what extent nondeterminism influences the result, i.e. to what extent the algorithm is determinate.

The result of the algorithm clearly depends on the partition of output signals that has to be chosen initially. In general, it also depends on the order of computation steps. We prove that for live marked graphs — a subclass of Petri nets of definite practical importance in the area of circuit design — the decomposition result depends only on the signal partition. In the proof, we also characterise redundant places in these marked graphs as shortcut places; this easy-to-apply graph-theoretic characterisation is of independent interest.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [Ber87]
    Berthelot, G.: Transformations and decompositions of nets. In: Brauer, W., Reisig, W., Rozenberg, G., et al. (eds.) APN 1986. LNCS, vol. 254, pp. 359–376. Springer, Heidelberg (1987)Google Scholar
  2. [Bes87]
    Best, E.: Structure theory of Petri nets: The free choice hiatus. In: Brauer, W., Reisig, W., Rozenberg, G. (eds.) APN 1986. LNCS, vol. 254, pp. 168–205. Springer, Heidelberg (1987)Google Scholar
  3. [BN98]
    Baader, F., Nipkow, T.: Term Rewriting and All That. Cambridge University Press, Cambridge (1998)Google Scholar
  4. [CCJS94]
    Campos, J., Colom, J.M., Jungnitz, H., Silva, M.: Approximate throughput computation of stochastic marked graphs. IEEE Transactions on Software Engineering 20, 526–535 (1994)CrossRefGoogle Scholar
  5. [Chu87]
    Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis. MIT (1987)Google Scholar
  6. [CKK+97]
    Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Information and Systems E80-D, 3, 315–325 (1997)Google Scholar
  7. [DE95]
    Desel, J., Esparza, J.: Free Choice Petri Nets. Cambridge University Press, Cambridge (1995)MATHCrossRefGoogle Scholar
  8. [STC98]
    Silva, M., Teruel, E., Colom, J.M.: Linear algebraic and linear programming techniques for the analysis of place/transition net systems. In: Reisig, W., Rozenberg, G. (eds.) APN 1998. LNCS, vol. 1491, pp. 309–373. Springer, Heidelberg (1998)Google Scholar
  9. [VW02]
    Vogler, W., Wollowski, R.: Decomposition in asynchronous circuit design. In: Cortadella, J., Yakovlev, A., Rozenberg, G. (eds.) Concurrency and Hardware Design. LNCS, vol. 2549, pp. 152–190. Springer, Heidelberg (2002)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Mark Schäfer
    • 1
  • Walter Vogler
    • 1
  • Petr Jančar
    • 2
  1. 1.Institut für InformatikUniversität Augsburg 
  2. 2.Centre for Applied CyberneticsTechnical University of Ostrava 

Personalised recommendations