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A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures

  • P. M. Kelly
  • T. M. McGinnity
  • L. P. Maguire
  • L. M. McDaid
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3512)

Abstract

Field Programmable Gate Arrays (FPGAs) are being used as platforms for the digital implementation of intelligent systems. Binary digital systems provide an accurate, robust, stable performance that is free from the drift and manufacturing tolerances associated with analogue systems. However binary systems have a much lower functional density than their analogue counterparts resulting in inefficient use of silicon surface area. A design for a novel Configurable Logic Block (CLB) is presented which retains the robust qualities of digital processing whilst providing increased functional density. The circuit design uses Si/SiGe Inter-band Tunneling Diodes (ITDs) and NMOS/CMOS transistors to create quaternary memory cells in a topology and architecture suited to the implementation of neural networks. The performance of the CLB is simulated in HSPICE and the results are presented.

Keywords

Field Programmable Gate Array Negative Differential Resistance NMOS Transistor Resonant Tunnelling Diode Manufacturing Tolerance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Kelly, P.M., Thompson, C.J., McGinnity, T.M., Maguire, L.P.: Investigation of a Programmable Threshold Logic Gate Array. In: IEEE International Conference Electronics Circuits and Systems, proceedings, vol. II, pp. 673–767 (September 2002)Google Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • P. M. Kelly
    • 1
  • T. M. McGinnity
    • 1
  • L. P. Maguire
    • 1
  • L. M. McDaid
    • 1
  1. 1.Intelligent Systems Engineering Laboratory, Faculty of EngineeringUniversity of Ulster DerryUK

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