2-D Discrete Cosine Transform (DCT) on Meshes with Hierarchical Control Modes
An effective matrix operation is critical to process 2-D DCT. This paper presents a hierarchically controlled SIMD array (HCSA) well suited to matrix computations, in which a conventional 2-D torus is enhanced with the hierarchical organization of control units and the global data buses running across the rows and columns. The distinguished features of the HCSA are the diagonally indexed concurrent broadcast and the efficient data exchanges among PEs through either row or column broadcast. Therefore, the HCSA can provide significant improvement on computation steps of DCT. For the performance evaluation, an algorithmic mapping method is used and the number of computation steps is analytically compared with semisystolic architecture.
KeywordsDiscrete Cosine Transform Systolic Array Discrete Cosine Transform Coefficient Inverse Discrete Cosine Transform Host Processor
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- 1.Smith, R., Fant, K., Parker, D., Stephani, R., Ching-Yi, W.: An Asynchronous 2-D Discret Cosine Transform Chip. In: Proc. Int’l Symp. Asynchronous Circuits and Systems, pp. 224–233 (1998)Google Scholar
- 4.Sheu, M., Lee, J., Wang, J., Suen, A., Liu, L.: A High Throughput-rate Architecture for 8×8 2D DCT. In: Proc. Int’l Symp. Circuits and Systems, vol. 3, pp. 1587–1590 (1993)Google Scholar
- 9.Kung, S.Y.: VLSI Array Processor. Printice Hall, Englewood Cliffs (1988)Google Scholar