Xilinx System Generator Based HW Components for Rapid Prototyping of Computer Vision SW/HW Systems

  • Ana Toledo
  • Cristina Vicente-Chicote
  • Juan Suardíaz
  • Sergio Cuenca
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3522)


This paper shows how the Xilinx System Generator can be used to develop hardware-based computer vision algorithms from a system level approach without the necessity of in-depth knowing neither a hardware description language nor the particulars of the hardware platform. Also, it is demonstrated that Simulink can be employed as a co-design and co-simulation platform for rapid prototyping of Computer Vision HW/SW systems. To do this, a library of optimized image processing components based on XSG and Matlab has been developed and tested in hybrid schemes including HW and SW modules. As a part of the testing, results of the prototyping and co-simulation of a HW/SW Computer Vision System for the automated inspection of tangerine segments are presented.


image processing applications FPGAs prototyping co-simulation Simulink 


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  1. 1.
    Arnout, G.: C for System Level Design. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (March 1999)Google Scholar
  2. 2.
    Panda, P.R.: SystemC - a modeling platform supporting multiple design abstractions. In: Proceedings of the 14th ISSS, pp. 75–80 (2001)Google Scholar
  3. 3.
    Hwang, J., Milne, B., Shirazi, N., Stroomer, J.: System Level Tools for DSP in FPGAs. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 534–543. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  4. 4.
    SystemC, Available:
  5. 5.
    System Generator: Reference guide,
  6. 6.
    DSP builder, Available:
  7. 7.
    The Math Works Inc.,
  8. 8.
    Líčko, M., Schier, J., Tichý, M., Kühl, M.: MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 984–987. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Denning, D., Harold, N., Devlin, M., Irvine, J.: Using System Generator to Design a Reconfigurable Video Encryption System. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 980–983. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  10. 10.
    Lisa, F., Cuadrado, F., Rexachs, D., Carrabina, J.: A reconfigurable coprocessor for a PCI-based real time computer vision system. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, pp. 392–399. Springer, Heidelberg (1997)CrossRefGoogle Scholar
  11. 11.
    Wang, K., Chia, T., Chen, Z., Lou, D.: Parallel Execution of a Connected Component Labeling Operation on a Linear Array Architecture. Journal of Information Science and Engineering 19, 353–370 (2003)Google Scholar
  12. 12.
    ModelSim, Available:
  13. 13.

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Ana Toledo
    • 1
  • Cristina Vicente-Chicote
    • 2
  • Juan Suardíaz
    • 1
  • Sergio Cuenca
    • 3
  1. 1.Departamento de Tecnología ElectrónicaUniversidad Politécnica de CartagenaSpain
  2. 2.Departamento de Tecnologías de la Información y ComunicacionesUniversidad Politécnica de CartagenaSpain
  3. 3.Departamento de Tecnología Informática y ComputaciónUniversidad de AlicanteSpain

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