Advertisement

Eliminating Redundant Tests in a Checking Sequence

  • Jessica Chen
  • Robert M. Hierons
  • Hasan Ural
  • Husnu Yenigun
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3502)

Abstract

Under certain well–defined conditions, determining the correctness of a system under test (SUT) is based on a checking sequence generated from a finite state machine (FSM) specification of the SUT. When there is a distinguishing sequence for the FSM, an efficient checking sequence may be produced from the elements of a set E α of α′-sequences that verify subsets of states and the elements of a set E C of subsequences that test the individual transitions. An optimization algorithm may be used in order to produce a shortest checking sequence by connecting the elements of E α and E C using transitions drawn from an acyclic set. Previous work did not consider whether some transition tests may be omitted from E C . This paper investigates the problem of eliminating subsequences from E C for those transitions that correspond to the last transitions traversed when a distinguishing sequence is applied in an α′–sequence to obtain a further reduction in the length of a checking sequence.

Keywords

Input Sequence Transition Test Distinguishing Sequence System Under Test Conformance Testing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Tanenbaum, A.S.: Computer Networks, 3rd edn. Prentice Hall International Editions. Prentice Hall, Englewood Cliffs (1996)zbMATHGoogle Scholar
  2. 2.
    Pomeranz, I., Reddy, S.M.: Test generation for multiple state–table faults in finite–state machines. IEEE Transactions on Computers 46, 783–794 (1997)CrossRefGoogle Scholar
  3. 3.
    Hierons, R.M., Harman, M.: Testing conformance to a quasi–non–determinstic stream X–machine. Formal Aspects of Computing 12, 423–442 (2000)CrossRefzbMATHGoogle Scholar
  4. 4.
    Holcombe, M., Ipate, F.: Correct Systems: Building a Business Process Solution. Springer, Heidelberg (1998)CrossRefzbMATHGoogle Scholar
  5. 5.
    Luo, G., Das, A., van Bochmann, G.: Generating tests for control portion of SDL specifications. In: Proceedings of Protocol Test Systems VI, pp. 51–66. Elsevier (North-Holland), Amsterdam (1994)Google Scholar
  6. 6.
    Tan, Q.M., Petrenko, A., van Bochmann, G.: Modeling basic lotos by fsms for conformance testing. In: IFIP Protocol Specification, Testing, and Verification XV, pp. 137–152 (1995)Google Scholar
  7. 7.
    Ural, H., Saleh, K., Williams, A.: Test generation based on control and data dependencies within system specifications in SDL. Computer Communications 23, 609–627 (2000)CrossRefGoogle Scholar
  8. 8.
    van Bochmann, G., Petrenko, A., Bellal, O., Maguiraga, S.: Automating the process of test derivation from SDL specifications. In: SDL Forum 1997, Paris, France (1997)Google Scholar
  9. 9.
    International Telecommunications Union Geneva, Switzerland: Recommendation Z.500 Framework on formal methods in conformance testing (1997)Google Scholar
  10. 10.
    Moore, E.P.: Gedanken-experiments. In: Shannon, C., McCarthy, J. (eds.) Automata Studies. Princeton University Press, Princeton (1956)Google Scholar
  11. 11.
    Gonenc, G.: A method for the design of fault detection experiments. IEEE Transactions on Computers 19, 551–558 (1970)CrossRefzbMATHGoogle Scholar
  12. 12.
    Hennie, F.C.: Fault–detecting experiments for sequential circuits. In: Proceedings of Fifth Annual Symposium on Switching Circuit Theory and Logical Design, pp. 95–110. Princeton, New Jersey (1964)CrossRefGoogle Scholar
  13. 13.
    Hierons, R.M., Ural, H.: Reduced length checking sequences. IEEE Transactions on Computers 51, 1111–1117 (2002)MathSciNetCrossRefzbMATHGoogle Scholar
  14. 14.
    Ural, H., Wu, X., Zhang, F.: On minimizing the lengths of checking sequences. IEEE Transactions on Computers 46, 93–99 (1997)CrossRefzbMATHGoogle Scholar
  15. 15.
    Lee, D., Yannakakis, M.: Principles and methods of testing finite–state machines – a survey. Proceedings of the IEEE 84, 1089–1123 (1996)CrossRefGoogle Scholar
  16. 16.
    Lee, D., Yannakakis, M.: Testing finite state machines: state identification and verification. IEEE Trans. Computers 43, 306–320 (1994)MathSciNetCrossRefGoogle Scholar
  17. 17.
    Kohavi, I., Kohavi, Z.: Variable-length distinguishing sequences and their application to the design of fault–detection experiments. IEEE Transactions on Computers, 792–795 (1968)Google Scholar
  18. 18.
    Garey, M.R., Johnson, D.S.: Computers and Intractability. W. H. Freeman and Company, New York (1979)zbMATHGoogle Scholar
  19. 19.
    Bar-Yehuda, R., Geiger, D., Naor, J., Roth, R.: Approximation algorithms for the vertex feedback set problem with applications to constraint satisfaction and bayesian inference. In: Proceedings of Fifth ACM-SIAM Symposium on Discrete Algorithms, pp. 344–354 (1994)Google Scholar
  20. 20.
    Fujito, T.: A note on approximation of the vertex cover and feedback vertex set problems. Information Processing Letters 59, 59–63 (1996)MathSciNetCrossRefzbMATHGoogle Scholar
  21. 21.
    Hierons, R.M., Ural, H.: Optimizing the length of checking sequences (submitted)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2005

Authors and Affiliations

  • Jessica Chen
    • 1
  • Robert M. Hierons
    • 2
  • Hasan Ural
    • 3
  • Husnu Yenigun
    • 4
  1. 1.School of Computer ScienceUniversity of WindsorWindsorCanada
  2. 2.Department of Information Systems and ComputingBrunel UniversityUxbridge, MiddlesexUK
  3. 3.School of Information Technology and EngineeringUniversity of OttawaOttawaCanada
  4. 4.Faculty of Engineering and Natural SciencesSabanci UniversityTuzla, IstanbulTurkey

Personalised recommendations