Modelling SystemC Process Behavior by the UML Method State Machines

  • Elvinia Riccobene
  • Patrizia Scandurra
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3475)

Abstract

We describe the SystemC Process State Machines that we have defined, as a variation of the UML method state machines, to model the behavior of reactive processes of the SystemC language. They are part of a complete UML 2.0 profile for SystemC that we have developed to improve the SoC (System on a Chip) design flow in order to provide a modelling framework which allows high-level designing SoC components in the style of UML using the SystemC design primitives.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Elvinia Riccobene
    • 1
  • Patrizia Scandurra
    • 1
  1. 1.Dipartimento di Matematica e InformaticaUniversità di CataniaCataniaItaly

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