Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

  • Jaan Raik
  • Raimund Ubar
  • Sergei Devadze
  • Artur Jutman
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3463)

Abstract

Current paper proposes an efficient alternative for traditional gate-level fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations can be significantly reduced. In addition, algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper. While full implementation of the new SSBDD based algorithms needs to be carried out, the paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Jaan Raik
    • 1
  • Raimund Ubar
    • 1
  • Sergei Devadze
    • 1
  • Artur Jutman
    • 1
  1. 1.Department of Computer EngineeringTallinn University of TechnologyTallinnEstonia

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