An Approach to System-level Design for Test

  • G. Jervan
  • R. Ubar
  • Z. Peng
  • P. Eles
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

8.1 Abstract

In this chapter we will describe a Design-for-Test (DfT) methodology for systems-on-chip. We have developed a hybrid Built-In Self-Test (BIST) approach, where the test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated offline and stored in the system. We have analyzed the aspects related to the cost calculation of such a hybrid BIST approach and will propose a test cost minimization strategy for single-core designs. We have then extended the same approach for multi-core designs and developed a test time minimization methodology under tester memory constraints. We will demonstrate the applicability and efficiency of the proposed approach for cores with different core-level DfT structures and for systems with different system-level test architectures.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Agrawal VD, Kime CR, Saluja KK (1993) A tutorial on built-in self-test. IEEE Design and Test of Computers, (March): 69-77.Google Scholar
  2. [2]
    Bardell PH, McAnney WH, Savir J (1987) Built-in test for VLSI pseudorandom techniques. John Wiley and Sons.Google Scholar
  3. [3]
    Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In: Proc. IEEE Int. Symp. on Circuits and Systems, 663–698.Google Scholar
  4. [4]
    Chatterjee M, Pradhan DK (1995) A novel pattern generator for near-perfect fault-coverage. In: Proc. IEEE VLSI Test Symposium, 417–425.Google Scholar
  5. [5]
    Glover F (1986) Future paths for integer programming and links to artificial intelligence. Computers & Ops. Res., (5): 533–549.Google Scholar
  6. [6]
    Golomb SW (1982) Shift register sequences. Aegan Park Press, Laguna Hills.Google Scholar
  7. [7]
    Hellebrand S, Tarnick S, Rajski J, Courtois B (1992) Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers. In: Proc. IEEE Int. Test Conference, 120–129.Google Scholar
  8. [8]
    Hellebrand S, Wunderlich H-J, Hertwig A (1998) Mixed-mode BIST using embedded processors. Journal of Electronic Testing: Theory and Applications, (12): 127–138.CrossRefGoogle Scholar
  9. [9]
    Jervan G, Peng Z, Ubar R (2000) Test cost minimization for hybrid BIST. In: Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 283–291.Google Scholar
  10. [10]
    Jervan G, Peng Z, Ubar R, Kruus H (2002) A hybrid BIST architecture and its optimization for SOC testing. In: Proc. IEEE International Symposium on Quality Electronic Design, 273–279.Google Scholar
  11. [11]
    Jervan G, Eles P, Peng Z, Ubar R, Jenihhin M (2003) Test time minimization for hybrid BIST of core-based systems. In: Proc. 12th IEEE Asian Test Symposium, 318–323.Google Scholar
  12. [12]
    Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science, 220(4598): 671–680.MathSciNetGoogle Scholar
  13. [13]
    Lee K-J, Chen J-J, Huang C-H (1999) Broadcasting test patterns to multiple circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 18(12): 1793–1802.Google Scholar
  14. [14]
    Sugihara M, Date H, Yasuura H (2000) Analysis and minimization of test time in a combined BIST and external test approach. In: Proc. IEEE Design, Automation & Test In Europe Conference, 134–140.Google Scholar
  15. [15]
    Touba NA, McCluskey EJ (1995) Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST. In: Proc. IEEE Int. Test Conference, 674–682.Google Scholar
  16. [16]
    Tallinn Technical University (1999) Turbo Tester Reference Manual. Version 3.99.03, http://www.pld.ttu.ee/ttGoogle Scholar
  17. [17]
    Ubar R, Jervan G, Peng Z, Orasson E, Raidma R (2001) Fast test cost calculation for hybrid BIST in digital systems. In: Proc. Euromicro Symposium on Digital Systems Design, 318–325.Google Scholar
  18. [18]
    Ubar R, Kruus H, Jervan G, Peng Z (2001) Using Tabu search method for optimizing the cost of hybrid BIST. In: Proc. 16th Conference on Design of Circuits and Integrated Systems, 445–450.Google Scholar
  19. [19]
    Ubar R, Jenihhin M, Jervan G, Peng Z (2004) Hybrid BIST optimization for core-based systems with test pattern broadcasting. In: Proc. IEEE Int. Workshop on Electronic Design, Test and Applications, 3–8.Google Scholar
  20. [20]
    Yarmolik VN, Kachan IV (1993) Self-checking VLSI design. Elsevier Science LtdGoogle Scholar
  21. [21]
    Zacharia N, Rajski J, Tyzer J (1995) Decompression of test data using variable-length seed LFSRs. IN: Proc. IEEE 13th VLSI Test Symposium, 426–433.Google Scholar

Copyright information

© Springer-Verlag London Limited 2005

Authors and Affiliations

  • G. Jervan
    • 1
    • 2
  • R. Ubar
    • 1
    • 2
  • Z. Peng
    • 1
    • 2
  • P. Eles
    • 1
    • 2
  1. 1.Linköping UniversityLinköpingSweden
  2. 2.Tallinn University of TechnologyTallinnEstonia

Personalised recommendations