Test Generation: A Hierarchical Approach

  • G. Jervan
  • R. Ubar
  • Z. Peng
  • P. Eles
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

5.1 Abstract

Advances in design tools and methods have led to an increasing amount of design activities being performed at higher levels of abstraction. Testability, on the other hand, is usually considered only when the detailed structural information of the design is available. This is mainly due to the lack of general applicability of the existing high-level test generation and design-for-test methods. In this chapter we will present an improvement of the classical hierarchical test generation approach by extending it to the higher levels of abstraction, while still considering the structural information from the lower levels. The approach proposed makes successful use of both high-level fault models and the classical gate-level fault models, and obtains results that are better than those obtained by a pure high-level test generator.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Abraham JA (1986) Fault modeling in VLSI. VLSI testing. North-Holland, 1–27Google Scholar
  2. [2]
    Brahme D, Abraham JA (1984) Functional testing of microprocessors. IEEE Transactions On Computers, 33(6): 475–485MATHGoogle Scholar
  3. [3]
    Bryant RE (1986) Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computers, 35(8): 667–690MathSciNetGoogle Scholar
  4. [4]
    Ghosh S, Chakraborty TJ (1991) On behavior fault modelling for digital designs. Journal of Electronic Testing: Theory and Applications, (2): 135–151CrossRefGoogle Scholar
  5. [5]
    Giambiasi N, Santucci JF, Courbis AL, Pla V (1991) Test pattern generation for behavioral descriptions in VHDL. In: Proc. of the VHDL conference, 228–234Google Scholar
  6. [6]
    Gupta AK, Armstrong JR (1985) Functional fault modeling and simulation for VLSI devices. In: 22nd Design Automation Conference, 720–726Google Scholar
  7. [7]
    Jervan G, Eles P, Peng Z (1999) A hierarchical test generation technique for embedded systems. In: Proc. Electronic Circuits and Systems Conference, 21–24Google Scholar
  8. [8]
    Jervan G, Peng Z, Goloubeva O, Sonza Reorda M, Violante M (2002) High-level and hierarchical test sequence generation. In: Proc. of IEEE International Workshop on High Level Design Validation and Test, 169–174Google Scholar
  9. [9]
    Minato S (1996) BDDs and applications for VLSI CAD. Kluwer Academic PublishersGoogle Scholar
  10. [10]
    Murray BT, Hayes JP (1998) Hierarchical test generation using precomputed tests for modules. In: Proc. IEEE International Test Conference, 221–229Google Scholar
  11. [11]
    Raik J, Ubar R (1999) Sequential circuit test generation using decision diagram models. In: Proc. of IEEE Design Automation and Test in Europe, 736–740Google Scholar
  12. [12]
    Shen L, Su SYH (1988) A functional testing method for microprocessors. IEEE Transactions on Computers, 37(10): 1288–1293CrossRefGoogle Scholar
  13. [13]
    Su SYH, Lin T (1984) Functional testing techniques for digital LSI/VLSI systems. In: 21st ACM/IEEE Design Automation Conference, 517–528Google Scholar
  14. [14]
    Thatte SM, Abraham JA (1980) Test generation for microprocessors. IEEE Transactions on Computers, 29(6): 429–441MathSciNetMATHGoogle Scholar
  15. [15]
    Ubar R (1996) Test synthesis with alternative graphs. IEEE Design&Test of Computers, Spring 1996: 48–57Google Scholar
  16. [16]
    Ubar R (1998) Multi-valued simulation of digital circuits with structurally synthesized binary decision diagrams. Multiple Valued Logic, 4: 141–157MATHGoogle Scholar
  17. [17]
    Ubar R (1998) Combining functional and structural approaches in test generation for digital systems. Microelectronics Reliability, 38(3): 317–329CrossRefGoogle Scholar
  18. [18]
    Ward PC, Armstrong JR (1990) Behavioral fault simulation in VHDL. In: 27th ACM/IEEE Design Automation Conference, 587–593Google Scholar

Copyright information

© Springer-Verlag London Limited 2005

Authors and Affiliations

  • G. Jervan
    • 1
    • 2
  • R. Ubar
    • 1
    • 2
  • Z. Peng
    • 1
    • 2
  • P. Eles
    • 1
    • 2
  1. 1.Linköping UniversityLinköpingSweden
  2. 2.Tallinn University of TechnologyTallinEstonia

Personalised recommendations